Patents by Inventor Tadashi Iijima

Tadashi Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389706
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.
    Type: Grant
    Filed: May 20, 2024
    Date of Patent: August 12, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Patent number: 12349482
    Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: July 1, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Taizo Takachi, Yuichi Yamamoto, Suguru Saito, Satoru Wakiyama, Yoichi Ootsuka, Naoki Komai, Kaori Takimoto, Tadashi Iijima, Masaki Haneda, Masaya Nagata
  • Patent number: 12317627
    Abstract: Provided is a semiconductor apparatus that can realize further enhancement of capabilities regarding a stacked structure of plural substrates. The semiconductor apparatus includes a first substrate that includes a first element layer including a first active element, and a first wiring layer arranged on the first element layer; and a second substrate that includes a second element layer including a second active element arranged on the first wiring layer, and a second wiring layer arranged on the second element layer, in which the first substrate and the second substrate are stacked one on another, and the second active element is provided in a compound semiconductor substrate.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 27, 2025
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tadashi Iijima, Yuki Miyanami
  • Patent number: 12196029
    Abstract: A hinge device 1 comprises a damper hinge 2 and a gravity hinge 3. The gravity hinge 3 comprises a rotational force imparting mechanism 70 for converting gravity of the door 6 to rotational force to a closing direction when the door 6 rotates to the closing direction. The damper hinge 2 comprises a damper mechanism 30 for reducing the rotational force to the closing direction of the door 6. The damper mechanism 30 includes a linear damper 31 disposed to the first hinge member 10 and a first cam member 32 and includes a second cam member 35 disposed to the second hinge member 20. The linear damper 31 is positioned far from the shaft member 40 in an orthogonal direction to a shaft line of the shaft member 40 and is positioned along the shaft member 40. When the door 6 rotates to the closing direction and goes down, the linear damper 31 is shortened along with a cam action of the first cam member 32 and the second cam member 35.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 14, 2025
    Inventors: Tadashi Iijima, Kazuma Mori
  • Publication number: 20240423001
    Abstract: A solid-state imaging device includes: a pixel section that includes a transparent semiconductor formed in an effective pixel region of an insulator, an organic photoelectric conversion film formed on the transparent semiconductor on a side opposite to the insulator, and a transparent electrode formed on the organic photoelectric conversion film on a side opposite to the transparent semiconductor; a coupling section disposed in the insulator in a peripheral region around the effective pixel region, the coupling section being coupled to a circuit that supplies electricity to the transparent electrode; and a wiring line that electrically couples the transparent electrode and the coupling section to each other, and is formed by a transparent electrode material.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 19, 2024
    Inventors: TADASHI IIJIMA, RYOSUKE SUZUKI, IWAO YAGI, MASAHIRO JOEI, KENICHI MURATA
  • Publication number: 20240387583
    Abstract: The present disclosure relates to a photodetector and an electronic apparatus that can enhance their performance. Provided is a photodetector including multiple pixels each having a photoelectric conversion region, and an on-chip micro lens disposed for the pixels. In at least a part of a pixel section including n×n pixels, a first on-chip micro lens and a second on-chip micro lens different from the first on-chip micro lens are disposed. The present disclosure can be applied to CMOS solid-state image pickup devices, for example.
    Type: Application
    Filed: March 24, 2022
    Publication date: November 21, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuya FURUMOTO, Shinji NAKAGAWA, Michiko SAKAMOTO, Jun KUROIWA, Tadashi IIJIMA, Tetsuya MINAKAWA
  • Publication number: 20240304649
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
  • Patent number: 12080745
    Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 3, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Patent number: 12066505
    Abstract: The characteristics of a winding to be tested is allowed to be analyzed more easily and in a shorter time. A testing instrument 1 includes an impulse voltage application capacitor Cs having one end connected to an external terminal T2, a switch SW and a current limiting resistor Rs connected in series between another end of the impulse voltage application capacitor Cs and an external terminal T1, and a parameter calculator 5. The parameter calculator 5 calculates at least one of the value of the equivalent capacitor Cd, the value of the equivalent inductor Ld and the value of the equivalent resistor Rd by performing regression analysis using a measured value of a voltage Vcd in an analysis time period Ta from turning on of the switch SW to start of resonance based on the equivalent inductor Ld, the equivalent capacitor Cd and the equivalent resistor Rd pertaining to a winding 11.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: August 20, 2024
    Assignee: HIOKI E.E. CORPORATION
    Inventor: Tadashi Iijima
  • Publication number: 20240274641
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 15, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
  • Publication number: 20240274630
    Abstract: The present disclosure relates to a light detecting device and an electronic apparatus that can improve sensor characteristics. Provided is a light detecting device including a plurality of pixels each having a photoelectric conversion region, a structural body being formed in a lattice manner as viewed in plan on a semiconductor substrate in which the photoelectric conversion region is formed, the structural body having a first film including a first material and a second film including a second material different from the first material. The present disclosure is applicable to a CMOS solid-state imaging device, for example.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 15, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tadashi IIJIMA
  • Patent number: 12057462
    Abstract: Provided is a solid-state imaging device that includes a first substrate which includes a first semiconductor substrate and a first multi-layered wiring layer that are stacked, a second substrate which includes a second semiconductor substrate and a second multi-layered wiring layer that are stacked, and a third substrate which includes a third semiconductor substrate and a third multi-layered wiring layer that are stacked. The solid-state imaging device further includes a first coupling structure for electrically coupling a circuit of the first substrate and a circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or a predetermined wiring line in the third multi-layered wiring layer to each other.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: August 6, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
  • Patent number: 12027558
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Publication number: 20240204014
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate in which a plurality of pixels is arranged in a matrix, the semiconductor substrate including a plurality of photoelectric conversion sections that each generate electric charge corresponding to a light receiving amount by photoelectric conversion for each of the pixels; an inter-pixel separation section between the pixels adjacent to each other, electrically and optically separating the adjacent pixels from each other, and having a first refractive index; and an in-pixel separation section between the photoelectric conversion sections adjacent to each other inside each of the pixels, electrically separating the adjacent photoelectric conversion sections, and having a second refractive index, a difference between the second refractive index and a refractive index of the semiconductor substrate being smaller than a difference between the first refractive index and the refractive index of the semiconductor
    Type: Application
    Filed: March 28, 2022
    Publication date: June 20, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Michiko SAKAMOTO, Hiroshi TANAKA, Shogo OTANI, Takashi KOJIMA, Tadashi IIJIMA, Shota KITAMURA
  • Publication number: 20240194718
    Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
  • Patent number: 12006747
    Abstract: Provided is a sliding door device which can move a support shaft attached to a sliding door along an inclined portion of a rail by using a pull-in device. The rail (6a) is provided with the straight portion (11) for linearly guiding the support shaft attached to the sliding door (2) and the inclined portion (12) which is inclined with respect to the straight portion (11) and obliquely guides the support shaft. The straight portion (11) of the rail (6a) is provided with the pull-in device (15) which can capture a trigger (18) provided on the straight portion (11) of the rail (6a) and linearly move along the straight portion (11) of the rail (6a) when the sliding door (2) is closed. A pull-in force transmission part (20) for moving the support shaft along the inclined portion (12) of the rail (6a) is coupled to the pull-in device (15).
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 11, 2024
    Assignee: SUGATSUNE KOGYO CO., LTD.
    Inventors: Tadashi Iijima, Kazuma Mori, Takuma Komoto
  • Publication number: 20240186357
    Abstract: An imaging element according to the present disclosure includes a pixel, an overflow path, a pixel isolation unit, a pixel isolation electrode, an in-pixel isolation unit, and an in-pixel isolation electrode. The pixel includes a plurality of photoelectric conversion units formed in a semiconductor substrate having an interconnect region arranged on a front surface side and performs photoelectric conversion of incident light. The overflow path mutually transfers charges between the plurality of photoelectric conversion units. The pixel isolation unit is at a boundary of the pixel. The pixel isolation electrode is in the pixel isolation unit, and a first bias voltage is applied to the pixel isolation electrode. The in-pixel isolation unit isolates the plurality of photoelectric conversion units from each other. The in-pixel isolation electrode is arranged in the in-pixel isolation unit, and a second bias voltage is applied to the in-pixel isolation electrode.
    Type: Application
    Filed: January 31, 2022
    Publication date: June 6, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroshi TAKAHASHI, Shigehiro IKEHARA, Tadashi IIJIMA
  • Patent number: 12002833
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: June 4, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Patent number: 11955500
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 9, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
  • Patent number: 11948961
    Abstract: A solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda