Patents by Inventor Tadashi Iijima
Tadashi Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11594567Abstract: A solid-state imaging device includes first through third substrates. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked thereon. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked thereon. A coupling structure for electrically coupling at least two of the first through third substrates includes a via. The via exposes a predetermined wiring line in the second multi-layered wiring layer while exposing a portion of a predetermined wiring line in the first multi-layered wiring layer from a back surface side of the first substrate, or exposes a predetermined wiring line in the third multi-layered wiring layer while exposing a portion of the predetermined wiring line in the first multi-layered wiring layer or the second multi-layered wiring layer from the back surface.Type: GrantFiled: March 23, 2018Date of Patent: February 28, 2023Assignee: SONY GROUP CORPORATIONInventors: Tadashi Iijima, Takatoshi Kameshima, Ikue Mitsuhashi, Hiroshi Horikoshi, Hideto Hashiguchi, Reijiroh Shohji, Minoru Ishida, Masaki Haneda
-
Publication number: 20230036325Abstract: The characteristics of a winding to be tested is allowed to be analyzed more easily and in a shorter time. A testing instrument 1 includes an impulse voltage application capacitor Cs having one end connected to an external terminal T2, a switch SW and a current limiting resistor Rs connected in series between another end of the impulse voltage application capacitor Cs and an external terminal T1, and a parameter calculator 5. The parameter calculator 5 calculates at least one of the value of the equivalent capacitor Cd, the value of the equivalent inductor Ld and the value of the equivalent resistor Rd by performing regression analysis using a measured value of a voltage Vcd in an analysis time period Ta from turning on of the switch SW to start of resonance based on the equivalent inductor Ld, the equivalent capacitor Cd and the equivalent resistor Rd pertaining to a winding 11.Type: ApplicationFiled: July 12, 2022Publication date: February 2, 2023Inventor: Tadashi IIJIMA
-
Publication number: 20230020137Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: ApplicationFiled: September 27, 2022Publication date: January 19, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
-
Publication number: 20220359603Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, HIROSHI HORIKOSHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, MASAKI HANEDA
-
Publication number: 20220359599Abstract: Provided is a semiconductor apparatus that can realize further enhancement of capabilities regarding a stacked structure of plural substrates. The semiconductor apparatus includes a first substrate that includes a first element layer including a first active element, and a first wiring layer arranged on the first element layer; and a second substrate that includes a second element layer including a second active element arranged on the first wiring layer, and a second wiring layer arranged on the second element layer, in which the first substrate and the second substrate are stacked one on another, and the second active element is provided in a compound semiconductor substrate.Type: ApplicationFiled: June 26, 2020Publication date: November 10, 2022Inventors: TADASHI IIJIMA, YUKI MIYANAMI
-
Publication number: 20220359605Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
-
Publication number: 20220352226Abstract: A semiconductor apparatus that makes it possible to suppress propagation of noise and heat between elements formed in upper and lower substrates in a stacked structure of plural substrates and suppress deterioration of characteristics of the elements is provided. The semiconductor apparatus includes: a first substrate including a first element layer including a first active element, a first wiring layer arranged on the first element layer, and a shield layer including an electrically conductive material arranged on the first wiring layer; and a second substrate including a second element layer including a second active element arranged on the shield layer, and a second wiring layer arranged on the second element layer, in which the first substrate and the second substrate are stacked one on another.Type: ApplicationFiled: June 26, 2020Publication date: November 3, 2022Inventors: TOSHIHIKO MIYAZAKI, YUKI KAWAHARA, TSUYOSHI SUZUKI, TADASHI IIJIMA
-
Patent number: 11476294Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: GrantFiled: March 29, 2021Date of Patent: October 18, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
-
Publication number: 20220310680Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Taizo TAKACHI, Yuichi YAMAMOTO, Suguru SAITO, Satoru WAKIYAMA, Yoichi OOTSUKA, Naoki KOMAI, Kaori TAKIMOTO, Tadashi IIJIMA, Masaki HANEDA, Masaya NAGATA
-
Publication number: 20220267995Abstract: An engine control system controls a work machine including an engine, a fuel injection device that injects fuel into the engine, and a hydraulic pump that is driven by the engine. The rotation state amount specification unit specifies a rotation state amount related to rotation of the engine. The injection amount determination unit determines a fuel injection amount by the fuel injection device based on the rotation state amount.Type: ApplicationFiled: September 18, 2020Publication date: August 25, 2022Applicant: Komatsu Ltd.Inventors: Tadashi Iijima, Tomoyuki Matsuda, Keiichi Arai
-
Patent number: 11411036Abstract: A solid-state imaging device includes a first substrate including a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate, a second substrate including a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate, a third substrate including a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate, and a first coupling structure for electrically coupling the first substrate and the second substrate. The first substrate, the second substrate, and the third substrate are stacked in this order. The first substrate and the second substrate are bonded together such that the first multi-layered wiring layer and the second multi-layered wiring layer are opposed to each other. The first substrate excludes a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.Type: GrantFiled: March 23, 2018Date of Patent: August 9, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
-
Patent number: 11411037Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: GrantFiled: March 23, 2018Date of Patent: August 9, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
-
Patent number: 11408218Abstract: Provided is a sliding door device which is capable of retracting a sliding door diagonally. Such a sliding door device 1 includes rails 7a and 7b for guiding the sliding door 2 to move in a retracting direction A from an open position to a closed position with respect to a main body 3 and guiding the sliding door 2 to move forward or backward in a front view of the sliding door 2 until reaching the closed position, a rod-shaped trigger 8 provided on one of the main body 3 and the sliding door 2, and a retracting device 9? provided on the other of the main body 3 and the sliding door 2 and retracting the trigger 8 while sliding in an axial direction D of the trigger 8 so that the sliding door 2 can move forward or backward.Type: GrantFiled: September 4, 2019Date of Patent: August 9, 2022Assignee: SUGATSUNE KOGYO CO., LTD.Inventors: Tadashi Iijima, Kyosuke Uchino
-
Publication number: 20220241657Abstract: Provided is a golf club that allows for adjustment of the swing balance in relation to the whole golf club. A golf club head in one embodiment includes a club head and a grip. The club head has a sole portion provided with one or more attachment recesses to which weight attachment members with different weights are attachable, and the grip is provided with an attachment recess to which the weight attachment members with different weights are attachable. The weight attachment members with different weights are interchangeable between the one or more attachment recesses of the club head and between the one or more attachment recesses of the club head and the attachment recess of the grip.Type: ApplicationFiled: July 1, 2020Publication date: August 4, 2022Inventors: Takeshi KASAI, Atsushi IIJIMA, Tadashi TOYA, Kazuki TSUJIURA
-
Publication number: 20220228411Abstract: Provided is a sliding door device which can move a support shaft attached to a sliding door along an inclined portion of a rail by using a pull-in device. The rail (6a) is provided with the straight portion (11) for linearly guiding the support shaft attached to the sliding door (2) and the inclined portion (12) which is inclined with respect to the straight portion (11) and obliquely guides the support shaft. The straight portion (11) of the rail (6a) is provided with the pull-in device (15) which can capture a trigger (18) provided on the straight portion (11) of the rail (6a) and linearly move along the straight portion (11) of the rail (6a) when the sliding door (2) is closed. A pull-in force transmission part (20) for moving the support shaft along the inclined portion (12) of the rail (6a) is coupled to the pull-in device (15).Type: ApplicationFiled: May 27, 2020Publication date: July 21, 2022Applicant: SUGATSUNE KOGYO CO., LTD.Inventors: Tadashi IIJIMA, Kazuma MORI, Takuma KOMOTO
-
Publication number: 20220157877Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: ApplicationFiled: February 3, 2022Publication date: May 19, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
-
Publication number: 20220106824Abstract: A hinge device 1 comprises a dumper hinge 2 and a gravity hinge 3. The gravity hinge 3 comprises a rotational force imparting mechanism 70 for converting gravity of the door 6 to rotational force to a closing direction when the door 6 rotates to the closing direction. The dumper hinge 2 comprises a dumper mechanism 30 for reducing the rotational force to the closing direction of the door 6. The dumper mechanism 30 includes a linear dumper 31 disposed to the first hinge member 10 and a first cam member 32 and includes a second cam member 35 disposed to the second hinge member 20. The linear dumper 31 is positioned far from the shaft member 40 in an orthogonal direction to a shaft line of the shaft member 40 and is positioned along the shaft member 40. When the door 6 rotates, the linear dumper 31 is shortened.Type: ApplicationFiled: December 20, 2019Publication date: April 7, 2022Applicant: SUGATSUNE KOGYO CO., LTD.Inventors: Tadashi IIJIMA, Kazuma MORI
-
Patent number: 11289526Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: GrantFiled: March 23, 2018Date of Patent: March 29, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
-
Publication number: 20220085093Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
-
Publication number: 20210391372Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA