Abstract: In a method for manufacturing a semiconductor device according to an embodiment, a trench is formed in an outer peripheral portion of a chip region on a bonding surface of a support substrate, and a semiconductor substrate having a chip ring in the outer peripheral portions of the chip regions on an inside of a dicing line respectively and the support substrate are bonded to position the trench from above the chip ring to the inside of the dicing line. In the method for manufacturing a semiconductor device, furthermore, the semiconductor substrate and the support substrate which are bonded to each other are subjected to dicing along the dicing line.

Abstract: In a method for manufacturing a semiconductor device according to an embodiment, an epitaxial semiconductor layer is epitaxially grown on a semiconductor substrate, a photoelectric converting portion is formed on the epitaxial semiconductor layer, a wiring layer is formed on the epitaxial semiconductor layer after forming the photoelectric converting portion, a support substrate is bonded onto the wiring layer, and the semiconductor substrate is etched from an opposite surface side to a side for the bonding after the bonding. In the method for manufacturing a semiconductor device, an amorphous Si layer is formed on the opposite surface side of the epitaxial semiconductor layer after the etching and an antireflection film and a color filter are formed on the amorphous Si layer in sequence.

Abstract: A semiconductor device, includes a semiconductor substrate; and a solder bump part, which is formed on the semiconductor substrate and in which no grain boundary extends equal to or over ? of a diameter dimension of said solder bump part from an outer circumferential surface between an end of a connection part with the semiconductor substrate and a lateral portion.

Abstract: An EGR valve device includes a valve housing of which inside exhaust gas passes through, a poppet valve as a valve body accommodated in the valve housing, and a hydraulic servo actuator for driving the poppet valve to be opened and closed. The hydraulic servo actuator is provided by a three-port or four-port servo valve.

Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer.

Abstract: An EGR valve device includes a valve housing of which inside exhaust gas passes through, a poppet valve as a valve body accommodated in the valve housing, and a hydraulic servo actuator for driving the poppet valve to be opened and closed. The hydraulic servo actuator is provided by a three-port or four-port servo valve.

Abstract: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.

Abstract: A method for executing water jet peening for giving an impact force to a surface of a structure member by a crushing pressure of a water jet and cavitation and improving residual stress, or washing, or reforming said surface, wherein said water jet peening is executed so as to make a natural frequency of oscillation of said structure member and a excitation frequency of oscillation of water jet peening different from each other.

Abstract: A semiconductor device, includes a semiconductor substrate; and a solder bump part, which is formed on the semiconductor substrate and in which no grain boundary extends equal to or over ? of a diameter dimension of said solder bump part from an outer circumferential surface between an end of a connection part with the semiconductor substrate and a lateral portion.

Abstract: A method of producing an electronic component includes forming a film of a first metal above a substrate; converting partly the film of the first metal into a film containing a second metal by replacement of at least part of the first metal with the second metal; forming a film of a third metal above the film containing the second metal; and removing the film of the first metal other than the film containing the second metal by wet etching using the film of the third metal as a mask.

Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Abstract: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.

Abstract: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.

Abstract: A method for executing water jet peening for giving an impact force to a surface of a structure member by a crushing pressure of a water jet and cavitation and improving residual stress, or washing, or reforming said surface, wherein said water jet peening is executed so as to make a natural frequency of oscillation of said structure member and a excitation frequency of oscillation of water jet peening different from each other.

Abstract: An exhaust gas recirculation system having an exhaust line connected to an exhaust manifold of an engine; an intake line connected to an intake manifold of the engine; and an EGR line that intercommunicates the exhaust line and the intake line, in which a part of exhaust gas exhausted from the exhaust line is delivered to the intake line via the EGR line to be recirculated in the engine, is provided with a liquid cooling heat exchanger made of a corrosion-resistant material at downstream of an intersection with the EGR line in the intake line.

Abstract: A semiconductor device and a method for making the semiconductor device having a barrier layer in a via hole region and a barrier layer in a via line region. The barrier layer in the via line region is initially thicker than the barrier layer in the via hole region, prior to being etched during an etching process due to varying selectivity of etching rates between the via hole region and the via line region.

Abstract: A semiconductor device is provided. The semiconductor device includes a region of closely packed lines and a region including an isolated line, separated by a region of carbon doped silicon oxide. As the surface of the semiconductor device is etched, the etching rate varies depending on the material being etched. Accordingly, the cross-sectional area of the isolated line must be adjusted to compensate for the slowed etching process in that region. The close packed lines may have a height, a, and a width, b thus having a cross-sectional area of a*b. However, the isolated line may have a height D*a, and a width, E*b, where D*E=1. Singular or multiple etching processes may used and the line widths adjusted accordingly.

Abstract: A semiconductor device and a method for making the semiconductor device having a barrier layer in a via hole region and a barrier layer in a via line region. The barrier layer in the via line region is initially thicker than the barrier layer in the via hole region, prior to being etched during an etching process due to varying selectivity of etching rates between the via hole region and the via line region.