Patents by Inventor Tadateru YAMADA

Tadateru YAMADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170125168
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventor: Tadateru YAMADA
  • Publication number: 20170062135
    Abstract: A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Inventors: Yukihiro FUJITA, Tadateru YAMADA
  • Patent number: 9576727
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1> about 0.15 and a condition of t3/t1> about 0.15 are satisfied.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 21, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tadateru Yamada
  • Patent number: 9530561
    Abstract: A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 27, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yukihiro Fujita, Tadateru Yamada
  • Patent number: 9448207
    Abstract: In a quality evaluation method, an evaluation substrate that includes a mounting region, in which a multilayer capacitor is to be mounted, in a center portion of the evaluation substrate is fixed in place using a plurality of fixed portions at corner portions of the evaluation substrate, each of which is a same distance from the mounting region. A voltage is applied to the multilayer capacitor mounted on the mounting region of the evaluation substrate. Sound is collected using a microphone that is near the multilayer capacitor mounted on the evaluation substrate.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: September 20, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto, Tadateru Yamada
  • Publication number: 20160093439
    Abstract: An electronic component includes an electronic element including two outer electrodes on surfaces thereof and a board terminal including a board main body and two mounting electrodes. The board main body has electrical insulating properties and a first principal surface. The two mounting electrodes are disposed on the first principal surface and electrically coupled to the two outer electrodes, respectively. The electronic element is mounted on the first principal surface side. The two outer electrodes are partially disposed outside an outer edge of the board terminal when viewed from the first principal surface side. The height from an end of each of the two outer electrodes opposite the board terminal to an end of the board terminal opposite the electronic element is not greater than a larger dimension of the width of the electronic element and the width of the board terminal.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 31, 2016
    Inventors: Yukihiro FUJITA, Tadateru YAMADA, Hirobumi ADACHI
  • Patent number: 9241408
    Abstract: In an electronic component, upper surface electrodes are located on one main surface of an insulating substrate of an interposer on which a multilayer ceramic capacitor is mounted. The insulating substrate has substantially the same shape as that of the multilayer ceramic capacitor, viewed from a direction perpendicular or substantially perpendicular to the main surface, and has the multilayer ceramic capacitor mounted thereon so that the length direction of the multilayer ceramic capacitor substantially coincides with the length direction of the insulating substrate. The insulating substrate includes cutouts that include connection electrodes, respectively, and that are located at the four corners viewed from the direction perpendicular or substantially perpendicular to the main surface. The upper surface electrodes on the one main surface are connected via the connection electrodes to lower surface electrodes, respectively, that are located on the other main surface and are connected to a circuit board.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: January 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Tadateru Yamada, Isamu Fujimoto
  • Publication number: 20150228409
    Abstract: A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.
    Type: Application
    Filed: February 9, 2015
    Publication date: August 13, 2015
    Inventors: Yukihiro FUJITA, Tadateru YAMADA
  • Publication number: 20150122537
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventor: Tadateru YAMADA
  • Publication number: 20140060192
    Abstract: In a quality evaluation method, an evaluation substrate that includes a mounting region, in which a multilayer capacitor is to be mounted, in a center portion of the evaluation substrate is fixed in place using a plurality of fixed portions at corner portions of the evaluation substrate, each of which is a same distance from the mounting region. A voltage is applied to the multilayer capacitor mounted on the mounting region of the evaluation substrate. Sound is collected using a microphone that is near the multilayer capacitor mounted on the evaluation substrate.
    Type: Application
    Filed: August 14, 2013
    Publication date: March 6, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Tadateru YAMADA
  • Publication number: 20130284507
    Abstract: In an electronic component, upper surface electrodes are located on one main surface of an insulating substrate of an interposer on which a multilayer ceramic capacitor is mounted. The insulating substrate has substantially the same shape as that of the multilayer ceramic capacitor, viewed from a direction perpendicular or substantially perpendicular to the main surface, and has the multilayer ceramic capacitor mounted thereon so that the length direction of the multilayer ceramic capacitor substantially coincides with the length direction of the insulating substrate. The insulating substrate includes cutouts that include connection electrodes, respectively, and that are located at the four corners viewed from the direction perpendicular or substantially perpendicular to the main surface. The upper surface electrodes on the one main surface are connected via the connection electrodes to lower surface electrodes, respectively, that are located on the other main surface and are connected to a circuit board.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Inventors: Kazuo HATTORI, Tadateru YAMADA, Isamu FUJIMOTO