Patents by Inventor Tadato Yamagata
Tadato Yamagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9503018Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: GrantFiled: November 17, 2015Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Publication number: 20160142011Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: ApplicationFiled: November 17, 2015Publication date: May 19, 2016Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
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Patent number: 9252793Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: GrantFiled: November 29, 2010Date of Patent: February 2, 2016Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Publication number: 20130314165Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: ApplicationFiled: November 29, 2010Publication date: November 28, 2013Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Publication number: 20120075029Abstract: There is provided a semiconductor device having resistance elements small in temperature dependence of the resistance value. The semiconductor device has metal resistance element layers. The metal resistance element layer includes a resistance film layer. The other metal resistance element layer includes another metal resistance film layer. The metal resistance film layer is one of titanium nitride resistance and tantalum nitride resistance. The other metal resistance film layer is the other of the titanium nitride resistance and the tantalum nitride resistance. The resistance value of titanium nitride resistance has a positive temperature coefficient. Whereas, the resistance value of tantalum nitride resistance has a negative temperature coefficient. A contact plug electrically couples the metal resistance film layer with the other metal resistance film layer.Type: ApplicationFiled: July 26, 2011Publication date: March 29, 2012Inventors: Yasushi SEKINE, Tadato Yamagata
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Patent number: 6859377Abstract: A dynamic associative memory device comprising memory cells each of that including: a capacitor connected to one of the bit lines through first transmission gate capable of being switched to ON by an activation of a word line, and having a cell plate supplied with a source voltage; at least one second transmission gate provided in series between the bit lines, capable of being switched to ON by a memory node potential at an opposite side of a source voltage supply-side of the capacitor; and a initializing circuit for controlling the memory node potential upon receiving a reset signal so that at least one of the second transmission gates is switched to OFF.Type: GrantFiled: September 24, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventor: Tadato Yamagata
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Patent number: 6844754Abstract: In a memory system having a data bus transferring data in either direction, highly reliable data transfer is provided regardless of the direction in which data is transferred. The signal lines of a data bus (12) bidirectionally transfer data. That is to say, during data write operations to a DIMM, the signal lines transfer data from a memory controller (10) to the DIMM, and during data read operations, they transfer data from the DIMM to the memory controller (10). The signal lines have, as terminating resistors, terminating variable resistors (VRt) whose impedance is controlled by the memory controller (10). During data write operations to the DIMM, the memory controller (10) sets the impedance of each terminating variable resistor (VRt) at a value suitable for writing, and during data read operations, it sets the impedance of each terminating variable resistor (VRt) at a value suitable for reading.Type: GrantFiled: November 20, 2002Date of Patent: January 18, 2005Assignee: Renesas Technology Corp.Inventor: Tadato Yamagata
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Publication number: 20040136216Abstract: A dynamic associative memory device comprising memory cells each of that including: a capacitor connected to one of the bit lines through first transmission gate capable of being switched to ON by an activation of a word line, and having a cell plate supplied with a source voltage; at least one second transmission gate provided in series between the bit lines, capable of being switched to ON by a memory node potential at an opposite side of a source voltage supply-side of the capacitor; and a initializing circuit for controlling the memory node potential upon receiving a reset signal so that at least one of the second transmission gates is switched to OFF.Type: ApplicationFiled: September 24, 2003Publication date: July 15, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Tadato Yamagata
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Publication number: 20030234664Abstract: In a memory system having a data bus transferring data in either direction, highly reliable data transfer is provided regardless of the direction in which data is transferred. The signal lines of a data bus (12) bidirectionally transfer data. That is to say, during data write operations to a DIMM, the signal lines transfer data from a memory controller (10) to the DIMM, and during data read operations, they transfer data from the DIMM to the memory controller (10). The signal lines have, as terminating resistors, terminating variable resistors (VRt) whose impedance is controlled by the memory controller (10). During data write operations to the DIMM, the memory controller (10) sets the impedance of each terminating variable resistor (VRt) at a value suitable for writing, and during data read operations, it sets the impedance of each terminating variable resistor (VRt) at a value suitable for reading.Type: ApplicationFiled: November 20, 2002Publication date: December 25, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Tadato Yamagata
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Patent number: 6650588Abstract: In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.Type: GrantFiled: June 25, 2002Date of Patent: November 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tadato Yamagata
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Patent number: 6643208Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in access with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.Type: GrantFiled: January 21, 2003Date of Patent: November 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
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Publication number: 20030189869Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of, an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.Type: ApplicationFiled: January 21, 2003Publication date: October 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
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Patent number: 6525984Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.Type: GrantFiled: January 17, 2002Date of Patent: February 25, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
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Publication number: 20030026155Abstract: In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.Type: ApplicationFiled: June 25, 2002Publication date: February 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Tadato Yamagata
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Patent number: 6515922Abstract: A memory module is provided with switch groups (SD0a to SD7a) in corresponding relation to data lines (DQ0 to DQ63) connected to memory devices (MD0 to MD7). The switch groups (SD0a to SD7a) connect all of the data lines (DQ0 to DQ63) to a portion external to the memory module (MMa) in a memory operation, and connect all of the data lines (DQ0 to DQ63) to inputs of an exclusive NOR circuit (EXa) after common 1-bit data is written into the memory devices (MD0 to MD7) in a testing operation. A malfunction of the memory devices (MD0 to MD7) is detected using an output signal (TMSa) from the exclusive NOR circuit (EXa). The memory module is accomplished which allows an inexpensive tester to conduct an electrical assembly check and a simple data write and read operation test upon the memory devices, which includes a small number of I/O pins for the check and test, and which does not deteriorate data input/output characteristics of the memory devices.Type: GrantFiled: July 21, 2000Date of Patent: February 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tadato Yamagata
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Publication number: 20020057618Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.Type: ApplicationFiled: January 17, 2002Publication date: May 16, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
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Patent number: 6341098Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.Type: GrantFiled: May 2, 2001Date of Patent: January 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
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Patent number: 6310815Abstract: Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.Type: GrantFiled: August 7, 1998Date of Patent: October 30, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Akira Yamazaki, Shigeki Tomishima, Yoshio Yukinari, Makoto Hatakenaka, Atsushi Miyanishi
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Publication number: 20010019502Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.Type: ApplicationFiled: May 2, 2001Publication date: September 6, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
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Patent number: RE39579Abstract: A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.Type: GrantFiled: June 4, 2001Date of Patent: April 17, 2007Assignee: Renesas Technology Corp.Inventors: Makoto Hatakenaka, Akira Yamazaki, Shigeki Tomishima, Tadato Yamagata