Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

Abstract: A first internal power supply circuit receiving an external power supply voltage for generating a first internal power supply voltage and a second internal power supply circuit receiving the external power supply voltage for generating a second internal power supply voltage are provided within a DRAM. A sense amplifier operates by the first internal power supply voltage. A write driver and a GIO line precharge circuit operate by the second internal power supply voltage. A peripheral circuit operates by the external power supply voltage. As a result, the sense amplifier and the peripheral circuit will not be affected by the operation of the write driver and the GIO line precharge circuit.

Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Abstract: Columns included in a sub-block are divided into first and second groups. If a defective memory cell column is present in the first group, an address comparison circuit activates a signal to select a redundant memory cell column, then selection prohibiting signal attains an "L" level based on information programmed in a programming circuit, a selection of a column in the first group is prohibited, and a redundant memory cell column selection signal is activated. Meanwhile, a normal selecting operation is performed to the second column group.

Abstract: A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.

Abstract: If a row (column) redundant circuit is not used, a comparison between a defective address and an internal address is not performed in a row (column) fuse programming portion in accordance with a signal output from a circuit for indicating if a row (column) redundant circuit is to be used or not. A comparison outcome signal which is generated when these addresses do not match each other is to be output from the row (column) fuse programming portion.

Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

Abstract: A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

Abstract: An SRAM includes a memory cell array, a peripheral circuitry including a bit line load connected to the memory cell array, a multiplexer and the like, and a voltage lowering circuit. The voltage lowering circuit receives a power supply potential Vcc and outputs a potential Vin which is lower. The potential Vin is applied to the peripheral circuitry except the memory cell array, and the power supply potential Vcc is directly applied to the memory cell array. Therefore, operational potential of the memory cell array is made relatively higher with respect to the peripheral circuitry. As a result, a static semiconductor memory device which can operation at low voltage and consumes less power can be provided.

Abstract: A static RAM includes: a memory cell array including word lines, bit line pairs and memory cells; a row recorder; a column decoder; a DTD signal generator responsive to transition of input data or transition of a write enable signal for generating a data transition detection signal for a prescribed time period; and a write driver responsive to the write enable signal and the data transition detection signal for supplying the input data to a bit line pair selected by the column decoder. Even when there is a noise in write enable signal during reading cycle and data transition detection signal is generated erroneously, erroneous writing of data can be prevented, since write enable signal is not supplied to the write driver.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup.

Abstract: A boosting circuit is provided applicable in various semiconductor integrated circuits such as a word line boosting circuit in a semiconductor memory. Because a backgate electrode of a PMOS transistor connected between power supply potential and an output node is connected to the output node, the output node is precharged to the Vcc level during a boosting term. Therefore, the boosting condition by a MOS capacitor is alleviated in comparison with a conventional boosting circuit. Proper boosting operation can be carried out even at a lower level of a supplied power supply voltage. Therefore, operable margin of power supply voltage is enlarged.

Abstract: A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.

Abstract: A dynamic type semiconductor memory device includes a pair of transistors provided in a signal line for transmitting a sense amplifier drive signal to sense amplifiers. The transistors of the pair are provided in parallel with each other, and are activated to couple the sense amplifiers to a source of generating the sense amplifier drive signal. One of the pair of transistors is made nonconductive in a refresh mode of operation. This arrangement reduces the peak value of a current for charging and/or discharging bit lines by the sense amplifiers in the refresh mode of operation, and reduces a noise on a power source line or a ground line at an on-board level, resulting in stable operation of a system.

Abstract: A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.