Patents by Inventor Tadayoshi Watanabe
Tadayoshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307359Abstract: A semiconductor memory device includes first memory layers and second memory layers arranged in alternation in a first direction. First memory layers and second memory layers include memory strings and first wirings connected to these memory strings in common. First memory layers and second memory layers include: signal amplifier circuits electrically connected to the first wirings; second wirings connected to the signal amplifier circuits; first switch transistors connected to the second wirings; third wirings electrically connected to the second wirings via the first switch transistors; and fourth wirings electrically connected to the second wirings without via the first switch transistors. The semiconductor memory device includes: first via-contact electrodes extending in the first direction and connected to the third wirings in first memory layers; and second via-contact electrodes extending in the first direction and connected to the fourth wirings in second memory layers.Type: ApplicationFiled: September 14, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Tadayoshi WATANABE, Kouji MATSUO
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Patent number: 9082866Abstract: A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film. The second isolation region includes a second trench and a second element isolation insulating film filled in the second trench. The first and the second element isolation insulating films have different properties.Type: GrantFiled: September 5, 2013Date of Patent: July 14, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi Sakaguchi, Hirokazu Sugiyama, Yoshihisa Fujii, Shinichi Sotome, Tadayoshi Watanabe, Koichi Matsuno, Naoki Kai
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Publication number: 20140239368Abstract: A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film. The second isolation region includes a second trench and a second element isolation insulating film filled in the second trench. The first and the second element isolation insulating films have different properties.Type: ApplicationFiled: September 5, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi SAKAGUCHI, Hirokazu Sugiyama, Yoshihisa Fujii, Shinichi Sotome, Tadayoshi Watanabe, Koichi Matsuno, Naoki Kai
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Publication number: 20140054754Abstract: Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized. Utilizing the material as a mask layer and subsequently removing the material enables a number of mask layers to be minimized in a subsequent filling operation (e.g., metallization). Material amenable to being in a first physical state and a second physical state is an optically reactive material. The optically reactive dielectric can comprise an element or compound which can act as an agent/catalyst in the optical conversion process along with any element or compound which can act as an accelerator for the optical reaction. Conversion can be brought about by exposure to electromagnetic radiation and/or application of thermal energy.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Tadayoshi Watanabe, Hideaki Masuda, Hideshi Miyajima
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Patent number: 8614510Abstract: A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided in the wiring trench, forming the metal wiring by removing the metal film outside the wiring trench, performing a hydrophobic treatment to the surface of the insulating film after the forming the metal wiring, and forming a metal cap selectively on an upper surface of the metal wiring by plating after the performing the hydrophobic treatment.Type: GrantFiled: March 18, 2010Date of Patent: December 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Tomizawa, Noriaki Matsunaga, Tadayoshi Watanabe, Shiro Mishima, Masako Kodera
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Patent number: 8044519Abstract: A method of fabricating a semiconductor device includes forming an insulating film above a semiconductor substrate, forming a concave portion in the insulating film, forming a precursor film including a predetermined metallic element on a surface of the insulating film, carrying out a heat treatment on the precursor film and the insulating film to react with each other, thereby forming an insulative barrier film mainly comprising a compound of the predetermined metallic element and a constituent element of the insulating film in a self-aligned manner at a boundary surface between the precursor film and the insulating film, removing an unreacted part of the precursor film after forming the barrier film, forming a conductive film comprising at least one of Ru and Co on the barrier film, depositing a wiring material film on the conductive film, and forming a wiring from the wiring material film to provide a wiring structure.Type: GrantFiled: December 11, 2008Date of Patent: October 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tadayoshi Watanabe, Takamasa Usui
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Publication number: 20110189850Abstract: A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.Type: ApplicationFiled: April 12, 2011Publication date: August 4, 2011Inventors: Takamasa USUI, Tadayoshi WATANABE
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Patent number: 7944053Abstract: A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.Type: GrantFiled: November 24, 2008Date of Patent: May 17, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takamasa Usui, Tadayoshi Watanabe
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Publication number: 20110108987Abstract: A semiconductor device, may include a first insulating layer formed on a semiconductor substrate, a contact provided in the first insulating layer, a second dielectric layer formed on the first insulating layer, the second insulating layer having lower dielectric constant than the first dielectric layer, a wiring formed in the second insulating layer and being electrically connected to the contact, a first barrier metal formed on a bottom of the contact and on a side surface of the wiring, and a second barrier metal formed on a side surface of the bottom and on the first barrier metal.Type: ApplicationFiled: October 5, 2010Publication date: May 12, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideyuki Tomizawa, Tadayoshi Watanabe, Noriaki Matsunaga
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Publication number: 20110097890Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metaType: ApplicationFiled: January 3, 2011Publication date: April 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takamasa USUI, Tadayoshi WATANABE, Hayato NASU
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Patent number: 7902068Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.Type: GrantFiled: December 19, 2007Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tadayoshi Watanabe, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu
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Patent number: 7888262Abstract: In one aspect of the present invention, A method for manufacturing a semiconductor device may include forming a first wiring in a first insulating layer on a base member, forming a second insulating layer on the first insulating layer, forming a first hole in the second insulating layer so as to reach the first wiring in the first insulating layer and a second hole in the second insulating layer so as to reach the first insulating layer, forming a via contact in the first hole, and forming a third insulating layer on the second insulating layer so as to shut the second hole.Type: GrantFiled: December 13, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Hayashi, Tadayoshi Watanabe
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Patent number: 7888253Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metaType: GrantFiled: December 14, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takamasa Usui, Tadayoshi Watanabe, Hayato Nasu
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Patent number: 7847405Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.Type: GrantFiled: May 8, 2009Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tadayoshi Watanabe, Yumi Hayashi, Takamasa Usui
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Publication number: 20100237501Abstract: A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided in the wiring trench, forming the metal wiring by removing the metal film outside the wiring trench, performing a hydrophobic treatment to the surface of the insulating film after the forming the metal wiring, and forming a metal cap selectively on an upper surface of the metal wiring by plating after the performing the hydrophobic treatment.Type: ApplicationFiled: March 18, 2010Publication date: September 23, 2010Inventors: Hideyuki Tomizawa, Noriaki Matsunaga, Tadayoshi Watanabe, Shiro Mishima, Masako Kodera
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Patent number: 7755202Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film.Type: GrantFiled: March 31, 2008Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Hayashi, Tadayoshi Watanabe, Takamasa Usui
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Publication number: 20090289366Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.Type: ApplicationFiled: May 8, 2009Publication date: November 26, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadayoshi WATANABE, Yumi HAYASHI, Takamasa USUI
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Publication number: 20090152736Abstract: A method of fabricating a semiconductor device includes forming an insulating film above a semiconductor substrate, forming a concave portion in the insulating film, forming a precursor film including a predetermined metallic element on a surface of the insulating film, carrying out a heat treatment on the precursor film and the insulating film to react with each other, thereby forming an insulative barrier film mainly comprising a compound of the predetermined metallic element and a constituent element of the insulating film in a self-aligned manner at a boundary surface between the precursor film and the insulating film, removing an unreacted part of the precursor film after forming the barrier film, forming a conductive film comprising at least one of Ru and Co on the barrier film, depositing a wiring material film on the conductive film, and forming a wiring from the wiring material film to provide a wiring structure.Type: ApplicationFiled: December 11, 2008Publication date: June 18, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadayoshi Watanabe, Takamasa Usui
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Publication number: 20090134517Abstract: A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.Type: ApplicationFiled: November 24, 2008Publication date: May 28, 2009Inventors: Takamasa USUI, Tadayoshi Watanabe
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Publication number: 20080311742Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.Type: ApplicationFiled: December 19, 2007Publication date: December 18, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadayoshi WATANABE, Yoshiaki Shimooka, Naofumi Nakamura, Hayato Nasu