Patents by Inventor Tadayoshi Watanabe

Tadayoshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080246155
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 9, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yumi Hayashi, Tadayoshi Watanabe, Takamasa Usui
  • Publication number: 20080146015
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted meta
    Type: Application
    Filed: December 14, 2007
    Publication date: June 19, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa USUI, Tadayoshi WATANABE, Hayato NASU
  • Publication number: 20080142989
    Abstract: In one aspect of the present invention, A method for manufacturing a semiconductor device may include forming a first wiring in a first insulating layer on a base member, forming a second insulating layer on the first insulating layer, forming a first hole in the second insulating layer so as to reach the first wiring in the first insulating layer and a second hole in the second insulating layer so as to reach the first insulating layer, forming a via contact in the first hole, and forming a third insulating layer on the second insulating layer so as to shut the second hole.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 19, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yumi Hayashi, Tadayoshi Watanabe
  • Patent number: 6787462
    Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Iijima, Tadayoshi Watanabe
  • Publication number: 20020142622
    Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Iijima, Tadayoshi Watanabe
  • Patent number: 6407453
    Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating layer and a metallic wiring layer formed on the semiconductor substrate; and an intermediate layer formed between the insulating layer and the metallic wiring layer in contact with both the insulating layer and the metallic wiring layer, wherein the intermediate layer contains the metallic material forming the metallic wiring layer, Si and O.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: June 18, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Sachiyo Ito, Takamasa Usui, Hisashi Kaneko, Masako Morita, Hirokazu Ezawa