Patents by Inventor Tae-Gyeong Chung
Tae-Gyeong Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9685400Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: January 29, 2016Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Patent number: 9484292Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: April 28, 2014Date of Patent: November 1, 2016Assignee: SAMSUNG ELECTRONICS CO. LTD.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Publication number: 20160148913Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: January 29, 2016Publication date: May 26, 2016Inventors: Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
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Patent number: 8928154Abstract: A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.Type: GrantFiled: January 6, 2012Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Won Kang, Young-Hee Song, Tae-Gyeong Chung, Nam-Seog Kim, Seung-Duk Baek
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Publication number: 20140339290Abstract: Provided is a wire bonding method. The method includes: positioning a capillary having a wire inserted on a substructure including at least three connection terminals spaced apart from each other; forming an adhesive ball at a tip of the wire; bonding the adhesive ball to one of the connection terminals by lowering the capillary; and connecting the other connection terminals to the same wire by moving the capillary.Type: ApplicationFiled: May 15, 2014Publication date: November 20, 2014Inventors: Won-Gil HAN, Byongjoo KIM, Sangyoung KIM, Tae-Gyeong CHUNG, Sungbok HONG
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Publication number: 20140235017Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Inventors: Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
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Publication number: 20140208850Abstract: A semiconductor device defect detecting apparatus including: a sensor disposed on semiconductor process equipment, the sensor configured to detect a signal emitted from a semiconductor device in contact with the semiconductor process equipment; and a signal analyzer configured to determine whether the semiconductor device is defective based on the detected signal in a predetermined frequency range.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Inventors: Geun-woo Kim, Hyun Kim, Yun-sik Yoo, Sang-jun Kim, Jae-yong Park, Tae-gyeong Chung
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Patent number: 8736035Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: March 5, 2013Date of Patent: May 27, 2014Assignee: Samsung Electronics Co. Ltd.Inventors: Tae-Joo Hwang, Tae-gyeong Chung, Eun-chul Ahn
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Publication number: 20130200515Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: March 5, 2013Publication date: August 8, 2013Inventors: Tae-Joo HWANG, Tae-gyeong Chung, Eun-chul Ahn
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Patent number: 8431442Abstract: A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.Type: GrantFiled: October 5, 2011Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Wook Park, Tae Gyeong Chung, Ho Geon Song, Won Chul Lim
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Patent number: 8421244Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: GrantFiled: September 3, 2010Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Publication number: 20120326307Abstract: A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements.Type: ApplicationFiled: June 27, 2012Publication date: December 27, 2012Inventors: Se-young JEONG, Sang-sick PARK, Tae-gyeong CHUNG, Tae-je CHO
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Publication number: 20120115307Abstract: A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.Type: ApplicationFiled: October 5, 2011Publication date: May 10, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Wook Park, Tae Gyeong Chung, Ho Geon Song, Won Chul Lim
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Publication number: 20120104631Abstract: A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Inventors: Sun-Won Kang, Young-Hee Song, Tae-Gyeong Chung, Nam-Seog Kim, Seung-Duk Baek
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Patent number: 8129221Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.Type: GrantFiled: August 2, 2011Date of Patent: March 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Patent number: 8115324Abstract: A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.Type: GrantFiled: November 13, 2008Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Won Kang, Young-Hee Song, Tae-Gyeong Chung, Nam-Seog Kim, Seung-Duk Baek
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Publication number: 20110294260Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.Type: ApplicationFiled: August 2, 2011Publication date: December 1, 2011Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Patent number: 8022555Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.Type: GrantFiled: May 7, 2008Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
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Patent number: 7923291Abstract: A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.Type: GrantFiled: July 28, 2009Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-Jung Yu, Eun-Chul Ahn, Tae-Gyeong Chung, Nam-Seog Kim
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Publication number: 20100327439Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn