Patents by Inventor Tae-Gyeong Chung

Tae-Gyeong Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7821139
    Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Eun-Chul Ahn, Tae-Gyeong Chung
  • Publication number: 20100022051
    Abstract: A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.
    Type: Application
    Filed: July 28, 2009
    Publication date: January 28, 2010
    Inventors: Hae-Jung Yu, Eun-Chul Ahn, Tae-Gyeong Chung, Nam-Seog Kim
  • Publication number: 20090278561
    Abstract: The probe card is comprised of a probe card wafer, a plurality of through via electrodes penetrating the probe card wafer; and a plurality of redistributed wiring probe needle structures, each being connected to the through via electrodes protruding from a surface of the probe card wafer.
    Type: Application
    Filed: December 8, 2008
    Publication date: November 12, 2009
    Inventors: Cha-jea Jo, Tae-gyeong Chung, Hoon-jung Kim, Nam-seog Kim, Chang-seong Jeon
  • Publication number: 20090127717
    Abstract: A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.
    Type: Application
    Filed: November 13, 2008
    Publication date: May 21, 2009
    Inventors: Sun-Won Kang, Young-Hee Song, Tae-Gyeong Chung, Nam-Seog Kim, Seung-Duk Baek
  • Patent number: 7485955
    Abstract: A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Ku Kang, Seok Goh, Jin-Ho Kim, Tae-Gyeong Chung, Yong-Jae Lee
  • Publication number: 20080277800
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Application
    Filed: May 7, 2008
    Publication date: November 13, 2008
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20080268579
    Abstract: A semiconductor chip package capable of improving reliability at a chip interconnection portion and improving reliability in a solder joint by reducing thermal and mechanical stresses at an external portion of the package including a solder ball land, and a method of fabricating the package are provided. The method of fabricating a semiconductor chip package includes providing a substrate; forming a first underfill on a first portion of the substrate; forming a second underfill at a chip interconnection portion of the substrate; and mounting a semiconductor chip on the chip interconnection portion using conductive bumps. In the method, the second underfill is formed of a material having a modulus higher than the first underfill.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 30, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Jung YU, Mu-Seob SHIN, Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
  • Publication number: 20080173999
    Abstract: A stack package and a method of manufacturing the same are provided. The stack package includes one or more interposers in which a semiconductor chip having a bonding pad are inserted, an interconnection terminal groove is formed due to a difference of the areas between the semiconductor chip and a cavity into which the semiconductor chip is inserted, and an interconnection terminal connected to the bonding pad is formed in the interconnection terminal groove. In the stack package, the interposers are stacked with one another and the interconnection terminals are connected to one another such that one or more semiconductor chips are stacked and electrically connected.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Soo CHUNG, Dong-Hyeon JANG, Tae-Gyeong CHUNG, Nam-Seog KIM, Seung-Kwan RYU
  • Publication number: 20080122084
    Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 29, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joo HWANG, Eun-Chul AHN, Tae-Gyeong CHUNG
  • Patent number: 7368811
    Abstract: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: May 6, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: In-Ku Kang, Tae-Gyeong Chung, Sang-Ho An
  • Patent number: 7335592
    Abstract: A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: February 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Seob Kim, Tae-Gyeong Chung
  • Publication number: 20060071317
    Abstract: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.
    Type: Application
    Filed: April 12, 2005
    Publication date: April 6, 2006
    Inventors: In-Ku Kang, Tae-Gyeong Chung, Sang-Ho An
  • Publication number: 20060033212
    Abstract: A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.
    Type: Application
    Filed: October 20, 2005
    Publication date: February 16, 2006
    Inventors: Hyeong-Seob Kim, Tae-Gyeong Chung
  • Patent number: 6982487
    Abstract: A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: January 3, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Seob Kim, Tae-Gyeong Chung
  • Publication number: 20050205975
    Abstract: A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 22, 2005
    Inventors: In-Ku Kang, Seok Goh, Jin-Ho Kim, Tae-Gyeong Chung, Yong-Jae Lee
  • Patent number: 6943438
    Abstract: In one embodiment, a memory card comprises a card substrate, at least one memory chip attached to the card substrate, a control chip mounted on the memory chip, bonding wires electrically connecting the chips with the card substrate, a passive device attached to the card substrate near the memory chip, and a molded body encapsulating the memory chip, the control chip, the bonding wires and the passive device. In addition, the memory card comprises an adhesive spacer interposed between the same-sized chips to secure a wire loop of the bonding wires.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: September 13, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Young Son, Se-Yong Oh, Tae-Gyeong Chung
  • Patent number: 6857470
    Abstract: The present invention provides a stacked chip package having at least one heat transfer wire. The heat transfer wire is disposed between the stacked chips and at least one end of each transfer wire is connected to a dummy pad provided on the board. Therefore, the heat generated by the chips and trapped between the chips can be effectively dissipated. The heat transfer wires can be formed on the uppermost chip of the stacked chips to enhance the heat dissipation. In addition, by controlling the number or the size of the heat transfer wire, the thermal characteristics of the stacked chip package can be modified.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: February 22, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jin Park, Tae-Gyeong Chung, Eun-Chul Ahn
  • Patent number: 6812578
    Abstract: According to various embodiments of the present invention, a bonding pad structure of a semiconductor device reduces damage caused by thermo-mechanical stress in beam lead bonding. A method of fabricating an improved bonding pad structure is also provided. A polysilicon film plate is preferably formed between a bonding pad metal layer and a dielectric layer. The polysilicon film plate absorbs external thermo-mechanical stress and improves the durability of the bonding pad in a bond pull test (BPT). The bonding between the bonding pad metal layer and the dielectric layer is also improved. Other features and advantages are also provided.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: November 2, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin Kim, Tae-Gyeong Chung, Nam-Seog Kim, Woo-Dong Lee, Jin-Hyuk Lee
  • Publication number: 20040196635
    Abstract: The present invention provides a stacked chip package having at least one heat transfer wire. The heat transfer wire is disposed between the stacked chips and at least one end of each transfer wire is connected to a dummy pad provided on the board. Therefore, the heat generated by the chips and trapped between the chips can be effectively dissipated. The heat transfer wires can be formed on the uppermost chip of the stacked chips to enhance the heat dissipation. In addition, by controlling the number or the size of the heat transfer wire, the thermal characteristics of the stacked chip package can be modified.
    Type: Application
    Filed: November 20, 2003
    Publication date: October 7, 2004
    Inventors: Hee-Jin Park, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20040188837
    Abstract: A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.
    Type: Application
    Filed: September 22, 2003
    Publication date: September 30, 2004
    Inventors: Hyeong-Seob Kim, Tae-Gyeong Chung