Abstract: A display device and a method of manufacturing the display device are provided. Moisture may be prevented from penetrating into the display device. The display device includes a substrate including a pixel area. A thin film transistor is formed on the substrate. A pixel electrode is connected to the thin film transistor and formed in the pixel area. A roof layer is formed on the pixel electrode. The roof layer is separated from the pixel electrode via a microcavity. A liquid crystal layer fills the microcavity. A liquid crystal injection hole is formed in the roof layer and exposes a portion of the microcavity. An encapsulation layer is formed on the roof layer. The encapsulation layer covers the liquid crystal injection hole and seals the microcavity for the pixel area. The encapsulation layer includes a multilayer structure.

Abstract: A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus.

Abstract: A light-emitting device according to an exemplary embodiment of the present invention includes a first conductivity-type semiconductor layer disposed on a substrate; an active layer disposed on the first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer disposed on the active layer; and an irregular convex-concave pattern disposed on a surface of the first conductivity-type semiconductor layer. The irregular convex-concave pattern includes convex portions and concave portions, and the convex portions have irregular heights and the concave portions have irregular depths. The first conductivity-type semiconductor layer including the irregular convex-concave pattern is exposed from the active layer and the second conductivity-type semiconductor layer.

Abstract: The disclosure is related to determining a network connection structure of devices in a target service place by a service server including a processor and a memory and located at a remote location from the target service place. In order to determine, subscriber information of a target subscriber may be obtained. Based on the subscriber information, public network information associated with the target subscriber may be obtained from predetermined network devices associated with the target subscriber. First devices may be detected based on the obtained subscriber information and the collected network information, wherein the first devices are belonging to the target subscriber and are located in the target subscriber's service place.

Abstract: Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. The semiconductor memory device may also include a peripheral circuit suitable for providing a plurality of operation voltages including an erase verify voltage to the plurality of strings, and a control logic suitable for controlling the peripheral circuit to adjust a voltage level of the erase verify voltage applied to a selected memory cell, from among the plurality of drain side memory cells and the plurality of source side memory cells, according to a distance between the selected memory cell and the pipe transistor when an erase verify operation is performed.

Abstract: Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more).

Abstract: The present invention provides a converter including a plurality of sub-modules connected in series to each other, wherein each of the sub-modules includes a first half-bridge unit including a first energy storage unit, and a plurality of first power semiconductors connected in parallel to the first energy storage unit and connected in series to each other; a second half-bridge unit including a second energy storage unit, and a plurality of second power semiconductors connected in parallel to the second energy storage unit and connected in series to each other; and an auxiliary circuit unit connecting the first half-bridge unit and the second half-bridge unit; wherein the auxiliary circuit unit includes a single third power semiconductor and a single diode.

Abstract: The photo mask includes a mask substrate, and a mask pattern formed to include a plurality of unit mask patterns which are arranged in a single line for a fine pattern formation. The unit mask pattern is configured to include a body portion positioned at a center and wing portions formed in a triangular shape at both sides of the body portion.

Abstract: The present invention relates to a converter for electric power having multiple sub-modules connected in series, the sub-modules having an energy storage unit and multiple power semiconductor circuits connected in parallel to the energy storage unit, and which causes an electric current to bypass a sub-module in case the breakdown of the sub-module occurs. To this end, the converter for electric power according to the present invention has multiple sub-modules connected to each other in series, the sub-modules having an energy storage unit and at least one power semiconductor circuit that is connected in parallel to the energy storage unit and comprises multiple power semiconductor switches and freewheeling diodes, wherein each of the sub-modules comprises a bypass switching unit, which is connected in parallel to any one of said at least one power semiconductor circuit, and bypasses an electric current via the bypass switching unit.

Abstract: A pattern mask for patterning a thin film includes a transparent or translucent substrate with a plurality of grooves formed thereon having a pitch of about 4.6 ?m to about 10.8 ?m.

Abstract: A display device and a method of manufacturing the display device are provided. Moisture may be prevented from penetrating into the display device. The display device includes a substrate including a pixel area. A thin film transistor is formed on the substrate. A pixel electrode is connected to the thin film transistor and formed in the pixel area. A roof layer is formed on the pixel electrode. The roof layer is separated from the pixel electrode via a microcavity. A liquid crystal layer fills the microcavity. A liquid crystal injection hole is formed in the roof layer and exposes a portion of the microcavity. An encapsulation layer is formed on the roof layer. The encapsulation layer covers the liquid crystal injection hole and seals the microcavity for the pixel area. The encapsulation layer includes a multilayer structure.

Abstract: Exemplary embodiments of the present invention disclose a method of fabricating a gallium nitride (GaN) based semiconductor device. The method includes growing GaN based semiconductor layers on a first surface of a GaN substrate to form a semiconductor stack, and separating at least a first portion of the GaN substrate from the semiconductor stack using a wire cutting technique.

Abstract: A method of manufacturing an electrowetting display device includes a preliminary partition wall pattern formed on a lower substrate on which a pixel electrode of an oxide series and an insulation layer are formed. The preliminary partition wall pattern is disposed along a boundary of the pixel electrode. A water-repellent layer including a self-assembled monolayer having a hydrophobic property is formed on the lower substrate. A portion of the preliminary partition wall pattern and the water-repellent layer formed on the preliminary partition wall pattern are removed to form a partition wall pattern on the insulation layer and to form a water-repellent pattern on the pixel electrode and the insulation layer between partition walls of the partition wall patterns. A fluid layer is formed on the lower substrate on which the water-repellent pattern is formed. The lower substrate and an upper substrate are combined with each other.

Abstract: An apparatus including a scintillator panel which absorbs X-rays radiated from an X-ray generator and converts the X-rays into visible light; an image detector including a plurality of pixels arranged in a matrix array and charging the plurality of pixels with electric charges proportional to intensity of the visible light converted by the scintillator panel; a gate driver which selects a line in the image detector and applies a drive signal to pixels in the selected line; an automatic exposure request signal generator which generates an automatic exposure request signal as a trigger signal informing of X-ray radiation through detection of X-rays radiated from the X-ray generator; and a controller which controls a time point of performing an exposure operation depending on a state of the drive signal applied to the pixels of the selected line in response to the automatic exposure request signal is disclosed.

Abstract: An apparatus including a scintillator panel which absorbs X-rays radiated from an X-ray generator and converts the X-rays into visible light; an image detector including a plurality of pixels arranged in a matrix array and charging the plurality of pixels with electric charges proportional to intensity of the visible light converted by the scintillator panel; a gate driver which selects a line in the image detector and applies a drive signal to pixels in the selected line; an automatic exposure request signal generator which generates an automatic exposure request signal as a trigger signal informing of X-ray radiation through detection of X-rays radiated from the X-ray generator; and a controller which controls a time point of performing an exposure operation depending on a state of the drive signal applied to the pixels of the selected line in response to the automatic exposure request signal is disclosed.

Abstract: An inkjet print head includes a jet assembly, a printed-circuit board and a barrier coating film. The jet assembly includes a nozzle plate including a jet orifice in a lower surface of the nozzle plate and through which ink is discharged, and an ink transfer pathway inside nozzle plate. The printed-circuit board is combined with the jet assembly. The printed-circuit board includes an integrated circuit and a connection electrode. The barrier coating film includes organic material, a flexible layer and a hydrophobic layer. The barrier coating film covers an inner and an outer surface of the jet assembly, and an outer surface of the printed-circuit board. The barrier coating film exposes the lower surface of the nozzle plate and an outer surface of the connection electrode.

Abstract: A display panel includes; a substrate, and a light blocking structure surrounding an ink filling region on the substrate, the light blocking structure including; a first layer pattern having an ink affinity characteristic disposed on the substrate, and a second layer pattern positioned on the first layer pattern and including an organic material having a light blocking characteristic.

Abstract: Provided is a display device capable of preventing a liquid crystal from being left outside a microcavity. The display device includes: a substrate; a pixel electrode formed on the substrate; a roof layer formed on the pixel electrode so as to be spaced apart from the pixel electrode with a plurality of microcavities therebetween; a light blocking member positioned between two microcavities of the plurality of microcavities, overlapping with a first edge of one microcavity of the two microcavities, and not overlapping with a second edge of the other microcavity; an injection hole exposing a part of the microcavity; a liquid crystal layer filling the microcavity; and an encapsulation layer formed on the roof layer so as to cover the injection hole to seal the microcavity.

Abstract: An apparatus including a scintillator panel which absorbs X-rays radiated from an X-ray generator and converts the X-rays into visible light; an image detector including a plurality of pixels arranged in a matrix array and charging the plurality of pixels with electric charges proportional to intensity of the visible light converted by the scintillator panel; a gate driver which selects a line in the image detector and applies a drive signal to pixels in the selected line; an automatic exposure request signal generator which generates an automatic exposure request signal as a trigger signal informing of X-ray radiation through detection of X-rays radiated from the X-ray generator; and a controller which controls a time point of performing an exposure operation depending on a state of the drive signal applied to the pixels of the selected line in response to the automatic exposure request signal is disclosed.

Abstract: Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. The semiconductor memory device may also include a peripheral circuit suitable for providing a plurality of operation voltages including an erase verify voltage to the plurality of strings, and a control logic suitable for controlling the peripheral circuit to adjust a voltage level of the erase verify voltage applied to a selected memory cell, from among the plurality of drain side memory cells and the plurality of source side memory cells, according to a distance between the selected memory cell and the pipe transistor when an erase verify operation is performed.