Abstract: An apparatus and methods for reducing overshoot and undershoot using a reconfigurable inductor in a switching voltage regulator. Specifically, the switching voltage regulator includes a reconfigurable inductor, the reconfigurable inductor has a conductive control ring, and the conductive control ring has an adjustable enclosed area controlled by at least a first switch, wherein the reconfigurable inductor has a varying inductance based on a state of at least the first switch and the adjustable enclosed area of the conductive control ring is shown.

Abstract: Disclosed is a brake master cylinder configured to sense a variation in magnetic flux in accordance with operation of a piston installed with a magnet, and thus to control activation of brake lamps. The brake master cylinder includes a cylinder body connected to a booster, first and second pistons to reciprocate in the cylinder body, a Hall sensor installed at an outside of the cylinder body, to sense operation of the pistons, for control of activation of brake lamps, a coupling shaft formed at an end of the second piston facing the first piston, and a magnet ring assembly installed at the coupling shaft such that the magnet ring assembly faces the Hall sensor. The magnet ring assembly includes a bushing centrally formed with a fitting hole to receive the coupling shaft, and a ring-shaped magnet fitted around the bushing, to exert magnetic force on the Hall sensor.

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract: A memory array includes segmented global and local digit lines in which the global digit line segments are switchably coupled to one of a plurality of local digit line segments at a time. A sense circuit coupled to a global digit line segment can be switched to sense memory cells coupled to one of the plurality of local digit lines at a first time and memory cells coupled to a second one of the plurality of local digit lines at a second time. Neither the global digit line segments nor the local digit line segments extend through the entire memory array.

Abstract: Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

Abstract: A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.

Abstract: A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.

Abstract: A system for providing power and ground vias for power distributions systems includes first and second conductive layers on a microelectronic package. The conductive layers may include one or more conductive components such as, but not limited to, power planes, ground planes, pads, traces, and the like for electrically connecting to electronic components. A via may electrically connect the first and second conductive layers. The via may have a cross-section of at least three partially-overlapping shapes. Each of the shapes partially overlaps at least two of the other shapes. The shapes may be, for example, circular, triangular, rectangular, square, polygonal, rhomboidal shape, or any other shape.

Abstract: An apparatus for loading and unloading a main landing gear (“MLG”) of an aircraft includes a fixture that is adapted to couple to a truck of the MLG such that a sagittal plane of the fixture is parallel to or coplanar with a sagittal plane of the MLG and both translational forces and turning moments applied to the fixture are coupled directly through the fixture to the MLG, a mechanism for controllably translating the fixture in the sagittal plane thereof, and a mechanism for controllably rotating the fixture in the sagittal plane thereof.

Abstract: Disclosed is a brake master cylinder configured to sense a variation in magnetic flux in accordance with operation of a piston installed with a magnet, and thus to control activation of brake lamps. The brake master cylinder includes a cylinder body connected to a booster, first and second pistons to reciprocate in the cylinder body, a Hall sensor installed at an outside of the cylinder body, to sense operation of the pistons, for control of activation of brake lamps, a coupling shaft formed at an end of the second piston facing the first piston, and a magnet ring assembly installed at the coupling shaft such that the magnet ring assembly faces the Hall sensor. The magnet ring assembly includes a bushing centrally formed with a fitting hole to receive the coupling shaft, and a ring-shaped magnet fitted around the bushing, to exert magnetic force on the Hall sensor.

Abstract: Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

Abstract: A method for improving the bioavailability of polysaccharides in lignocellulosic materials, involving reacting lignocellulosic materials with ammonia and ethanol.

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract: An apparatus for loading and unloading a main landing gear (“MLG”) of an aircraft includes a fixture that is adapted to couple to a truck of the MLG such that a sagittal plane of the fixture is parallel to or coplanar with a sagittal plane of the MLG and both translational forces and turning moments applied to the fixture are coupled directly through the fixture to the MLG, a mechanism for controllably translating the fixture in the sagittal plane thereof, and a mechanism for controllably rotating the fixture in the sagittal plane thereof.

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

Abstract: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

Abstract: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

Abstract: A universal glucometer connector system comprising: a glucometer for measuring glucose concentration of blood, and having a top, bottom and side surface; a jacket for retaining the glucometer; a first opening in the jacket for receiving a glucovial that can be one of a plurality of shapes and sizes.