Patents by Inventor Tae Hang Ahn

Tae Hang Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11676820
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 13, 2023
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Publication number: 20200402804
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Oh-Hyun KIM, Sung-Hwan AHN, Hae-Jung PARK, Tae-Hang AHN
  • Patent number: 10790150
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Publication number: 20200083055
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Oh-Hyun KIM, Sung-Hwan AHN, Hae-Jung PARK, Tae-Hang AHN
  • Patent number: 10522362
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Patent number: 10186597
    Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: January 22, 2019
    Assignee: SK Hynix Inc.
    Inventors: Tae-Hang Ahn, Oh-Hyun Kim, Seung-Beom Baek
  • Publication number: 20180350611
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Application
    Filed: December 11, 2017
    Publication date: December 6, 2018
    Inventors: Oh-Hyun KIM, Sung-Hwan AHN, Hae-Jung PARK, Tae-Hang AHN
  • Publication number: 20180182861
    Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 28, 2018
    Inventors: Tae-Hang AHN, Oh-Hyun KIM, Seung-Beom BAEK
  • Patent number: 9929249
    Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor structure including a pattern; forming an epitaxial layer having a first dopant concentration in the pattern; forming in-situ an interface layer having a second dopant concentration higher than the first dopant concentration, over the epitaxial layer; forming a metal silicide layer over the interface layer; and forming a metal plug over the metal silicide layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: March 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae-Hang Ahn, Oh-Hyun Kim, Seung-Beom Baek
  • Patent number: 9831344
    Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Oh-Hyun Kim, Seung-Beom Baek, Tae-Hang Ahn
  • Publication number: 20170186870
    Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 29, 2017
    Inventors: Oh-Hyun KIM, Seung-Beom BAEK, Tae-Hang AHN
  • Patent number: 9614084
    Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: April 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Oh-Hyun Kim, Seung-Beom Baek, Tae-Hang Ahn
  • Patent number: 9048218
    Abstract: A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 2, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung-Ryong Lee, Tae-Hang Ahn
  • Patent number: 8912068
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Ho Lee, Seung-Joon Jeon, Tae-Hang Ahn
  • Publication number: 20120302024
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 29, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young-Ho LEE, Seung-Joon JEON, Tae-Hang AHN
  • Patent number: 8253204
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Ho Lee, Seung-Joon Jeon, Tae-Hang Ahn
  • Publication number: 20110241106
    Abstract: A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.
    Type: Application
    Filed: November 4, 2010
    Publication date: October 6, 2011
    Inventors: Seung-Ryong LEE, Tae-Hang Ahn
  • Patent number: 7968912
    Abstract: A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: June 28, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Soo Kim, Hong-Seon Yang, Seung-Ho Pyi, Tae-Hang Ahn
  • Patent number: 7915108
    Abstract: A method for fabricating a semiconductor device includes forming a device isolation structure in a substrate to define active regions, forming a hard mask pattern to open a region defining an active region pattern and to cover the device isolation structure, forming the active region pattern by selectively recessing the device isolation structure formed in the opened region using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulation layer over the substrate to cover at least the active region pattern, and forming a gate electrode over the gate insulation layer to cover at least the active region pattern.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 29, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se-Aug Jang, Hong-Seon Yang, Tae-Hang Ahn
  • Publication number: 20110003450
    Abstract: A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.
    Type: Application
    Filed: December 23, 2009
    Publication date: January 6, 2011
    Inventors: Young-Ho LEE, Tae-Hang Ahn, Seung-Beom Baek, Jun-Hee Cho, Jeong-Seon Kim