Abstract: A semiconductor memory device includes a standby voltage providing unit. The standby voltage providing unit is configured to receive an external voltage, primarily clamp and secondarily clamp a predetermined voltage, and provide the predetermined voltage as an internal voltage, during a standby mode.

Abstract: A high voltage switch circuit includes a high voltage switch suitable for transferring a voltage of an input terminal to an output terminal in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for changing a swing level of a preliminary activation signal, and generating the activation signal and the inverted activation signal.

Abstract: A high voltage switch circuit includes a high voltage switch suitable for transferring a voltage of an input terminal to an output terminal in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for changing a swing level of a preliminary activation signal, and generating the activation signal and the inverted activation signal.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line.

Abstract: A semiconductor memory device includes a standby voltage providing unit. The standby voltage providing unit is configured to receive an external voltage, primarily clamp and secondarily clamp a predetermined voltage, and provide the predetermined voltage as an internal voltage, during a standby mode.

Abstract: A semiconductor memory device includes word lines stacked over a substrate having a plurality of memory block regions, select lines arranged over the word lines, vertical channel layers formed to penetrate through the select lines and the word lines and extending to the substrate, and a charge trap layer disposed between the word lines and the vertical channel layers, wherein the stacked word lines are separated by memory block groups that each include two or more memory block regions.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line.

Abstract: A semiconductor memory device includes a charge pump circuit for generating a pass pump voltage in response to a clock signal and a pump enable signal and a regulator circuit for maintaining the pass pump voltage in the same level as a program pass voltage during a program operation and discharging the program pass voltage during a verification operation so that the program pass voltage has the same level as a verification pass voltage.

Abstract: A voltage level converting circuit includes: a voltage level converting block configured to convert an input signal having a first voltage level into an output signal having a second voltage level; and a boosting block connected to an input stage and an inverting input stage of the voltage level converting block, and configured to provide a negative voltage to the input stage or the inverting input stage.

Abstract: A semiconductor memory device includes word lines stacked over a substrate having a plurality of memory block regions, select lines arranged over the word lines, vertical channel layers formed to penetrate through the select lines and the word lines and extending to the substrate, and a charge trap layer disposed between the word lines and the vertical channel layers, wherein the stacked word lines are separated by memory block groups that each include two or more memory block regions.

Abstract: A semiconductor memory device includes a charge pump circuit for generating a pass pump voltage in response to a clock signal and a pump enable signal and a regulator circuit for maintaining the pass pump voltage in the same level as a program pass voltage during a program operation and discharging the program pass voltage during a verification operation so that the program pass voltage has the same level as a verification pass voltage.

Abstract: A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a plurality of required driving impedance values such that the driving units can obtain the plurality of required driving impedance values by a combination thereof, and a driving control unit that independently controls the operation of the plurality of driving units so as to obtain the plurality of driving impedance values required.

Abstract: A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer.

Abstract: An apparatus for generating an internal voltage includes an output-voltage detecting unit for detecting a voltage level of an internal voltage, an oscillating unit for generating a periodic signal in response to a detection signal from the output-voltage level detecting unit, a first driving-voltage level detecting unit for detecting an increase of a voltage level of a driving voltage, a second driving-voltage level detecting unit for detecting a decrease of a voltage level of the driving voltage, a period control unit for controlling a period of the periodic signal in response to output signals of the first and second driving-voltage level detecting units, and a charge pumping unit for generating the internal voltage by charge-pumping the driving voltage in response to an output signal from the period control unit.

Abstract: An apparatus for generating an internal voltage includes an output-voltage detecting unit for detecting a voltage level of an internal voltage, an oscillating unit for generating a periodic signal in response to a detection signal from the output-voltage level detecting unit, a first driving-voltage level detecting unit for detecting an increase of a voltage level of a driving voltage, a second driving-voltage level detecting unit for detecting a decrease of a voltage level of the driving voltage, a period control unit for controlling a period of the periodic signal in response to output signals of the first and second driving-voltage level detecting units, and a charge pumping unit for generating the internal voltage by charge-pumping the driving voltage in response to an output signal from the period control unit.

Abstract: A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer.

Abstract: Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.

Abstract: A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a plurality of required driving impedance values such that the driving units can obtain the plurality of required driving impedance values by a combination thereof, and a driving control unit that independently controls the operation of the plurality of driving units so as to obtain the plurality of driving impedance values required.

Abstract: Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.