Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.

Abstract: A multilayer electronic component includes a capacitor body having first to six surfaces, the capacitor body including a dielectric layer and first and second internal electrodes having one ends exposed through the third and fourth sides, respectively, first and second external electrodes including first and second connection portions disposed on the third and fourth surfaces of the capacitor body, respectively, and first and second band portions spaced apart from each other on the first surface of the capacitor body, respectively, a first connection terminal disposed on the first band portion and having a first cutout disposed in a lower surface thereof, open toward the third surface of the capacitor body, and a second connection terminal disposed on the second band portion and having a second cutout formed in a lower surface thereof, open toward the fourth surface of the capacitor body.

Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.

Abstract: A multilayer capacitor and a board having the same mounted thereon are provided. The multilayer capacitor includes a capacitor body including dielectric layers and first and second internal electrodes, and first to sixth surfaces, the first internal electrode being exposed through the third surface and the fifth surface and the second internal electrode being exposed through the fourth surface and the sixth surface; first and second side portions disposed on the fifth and sixth surfaces, respectively, of the capacitor body; first and second external electrodes; a first step-compensating portion disposed on a margin portion in a width direction on the second dielectric layer on which the second internal electrode is formed on the first internal electrode; and a second step-compensating portion disposed on another margin portion in the width direction on the first dielectric layer on which the first internal electrode is disposed on the second internal electrode.

Abstract: A method for concealing original data to protect personal information is provided. The method includes steps of: a data obfuscation device (a) if the original data is acquired, inputting the original data or its modified data into a learning network, and allowing the learning network to (i) apply a network operation to the original data or the modified data using learned parameters of the learning network and thus to (ii) output characteristic information on the original data or the modified data; and (b) updating the original data or the modified data via backpropagation using part of (i) 1-st losses calculated by referring to the characteristic information and its corresponding 1-st ground truth, and (ii) 2-nd losses calculated by referring to (ii-1) a task specific output generated by using the characteristic information and (ii-2) a 2-nd ground truth corresponding to the task specific output, to thereby generate obfuscated data.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.

Abstract: Disclosed are a storage control method and a storage controller for a virtualization environment with which to provide a virtualization service. The disclosed storage control method may include adjusting an over-provisioning proportion for a virtual storage device allotted to each virtual machine according to an I/O workload pattern for each of the virtual machines; and allotting an over-provisioning space for each of the virtual storage devices according to the over-provisioning proportion.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: The memory controller includes a command generator generating first read commands respectively corresponding to each of a plurality of read voltages having different levels and transferring the first read commands to a memory device so that first read operation is performed plural times on a plurality of memory cells for each of the read voltages, and an inverted cell counter determining inverted cells showing different bit values during the first read operation performed plural times for each read voltage on the basis of read result data received from the memory device.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic and 40-50 at % of selenium. The electronic device may include a semiconductor memory device, the semiconductor memory device including a first memory cell that includes a first switching element. The first switching element may include a chalcogenide material including 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic, and 40-50 at % of selenium.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: A method drives an electronic device including a semiconductor memory in a test mode. The method includes applying a stress pulse simultaneously to a plurality of memory cells to turn on the plurality of memory cells, determining whether the memory cells are turned on or turned off, and applying a second maximum voltage to a selected memory cell of the plurality of memory cells only when the selected memory cell is determined to be in a turned-off state.

Abstract: There is provided a fluoride phosphor composite including: fluoride phosphor core particles that may be expressed by the empirical formula AxMFy:Mn4+, wherein A may be at least one selected from the group consisting of Li, Na, K, Rb, and Cs, M may be at least one selected from the group consisting of Si, Ti, Zr, Hf, Ge, and Sn, the composition ratio (x) of A may satisfy 2?x?3, the composition ratio (y) of F may satisfy 4?y?7, each fluoride phosphor composite particle may be coated with a Mn-free fluoride coating. The Mn-free fluoride coating may have a thickness less than or equal to 35% of the size of each fluoride phosphor composite particle.

Abstract: There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a plurality of coil layers and high-rigidity insulating layers disposed on and beneath the plurality of coil layers; and external electrodes disposed on external surfaces of the body and connected to the coil layers. Build-up insulating layers are disposed between the high-rigidity insulating layers to cover the coil layers, and the high-rigidity insulating layers have a Young's modulus greater than that of the build-up insulating layers.

Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.

Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.