Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: In an interface board for testing a multichip package, the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are electrically connected to terminals of the multichip package, the second surface includes lower terminals that are electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A semiconductor device including a substrate including a first and second region; a first active region formed in an upper portion of the substrate in the first region; a second active region formed in an upper portion of the substrate in the second region; a first gate structure extending across the first active region, having a first gate length, and including a first high-k dielectric layer, a first lower metal layer, and a first upper metal layer; a second gate structure extending across the second active region, having a second gate length, and including a second high-k dielectric layer, a second lower metal layer having at least one metal layer, and a second upper metal layer; and spacers at sides of each of the first and second gate structures, a cross section of each of the first and second high-k dielectric layers has a U-shape, a cross section of each of the first and second lower metal layers has a U-shape, the first and second lower metal layers covering bottom surfaces and inner side surfaces of

Abstract: In an interface board for testing a multichip package, the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are electrically connected to terminals of the multichip package, the second surface includes lower terminals that are electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract: The present invention relates to a pharmaceutical composition for the prevention and treatment of blood-brain barrier disorder comprising fluoxetine as an active ingredient. More particularly, fluoxetine inhibits the expressions of matrix metalloproteinase(MMP)-2, MMP-9, and MMP-12, which are reported to be related to blood-brain barrier (BBB) disruption and inflammatory reaction after spinal cord injury, specifically inhibits the activations of MMP-2 and MMP-9, inhibits the decomposition of ZO-1, the most representative tight junction protein, so as to maintain tight junction between endothelial cells and to protect blood-brain barrier thereby, inhibits the increase of blood-brain barrier permeability, and inhibits the expressions of chemoattractants of blood cells, such as CXCL-1, CXCL-2, CCL-2, CCL-3 and CCL-4 so as to reduce inflow of blood into spinal cord and recover exercise function which has been deteriorated by spinal cord injury.

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract: Provided are a semiconductor structure and a method of fabricating a semiconductor device. The method includes: preparing a substrate or an etch-target layer which is to be patterned; forming a first anti-reflective coating, which contains silsesquioxane resin and a cross-linking catalyst, on the substrate or the etch-target layer; forming an anti-penetration film and a second anti-reflective coating by causing a cross-linking reaction in a region of the first anti-reflective coating; and forming a photoresist pattern on the anti-penetration film.

Abstract: A photoresist composition includes a cyclic compound, a photoacid generator, and an organic solvent. The cyclic compound includes any one selected from the group consisting of moieties having chemical structures represented by the formulae (1), (2), (3) and (4) set forth herein, and at least one moiety having the chemical structure represented by the formula (9) set forth herein.

Abstract: An operational amplifier includes a differential amplifier for amplifying differential input signals to generate differential amplified signals. The operational amplifier also includes first and second single-ended amplifiers that each amplify the differential amplified signals to respectively generate first and second single-ended output signals that are differential with respect to each-other.

Abstract: A photoresist composition includes a cyclic compound, a photoacid generator, and an organic solvent. The cyclic compound includes any one selected from the group consisting of moieties having chemical structures represented by the formulae (1), (2), (3) and (4) set forth herein, and at least one moiety having the chemical structure represented by the formula (9) set forth herein.

Abstract: An operational amplifier includes a differential amplifier for amplifying differential input signals to generate differential amplified signals. The operational amplifier also includes first and second single-ended amplifiers that each amplify the differential amplified signals to respectively generate first and second single-ended output signals that are differential with respect to each-other.

Abstract: Disclosed is a polytrimethylene terephtalate conjugate fiber having high self-crimpability, which is prepared by conjugate-spinning two types of polytrimethylene terephtalates having different intrinsic viscosities in which a difference between the intrinsic viscosities ranges from 0.05 to 0.15 into a side-by-side fiber. Also, the polytrimethylene terephtalate conjugate fiber prepared by the conjugate-spinning undergoes a false twisting process, leading to development of three-dimensional high self crimpability and sufficient bulky property in the resulting fiber.