Abstract: Disclosed herein are a method for access control using real-time positioning technology and a device using the same. According to a positioning method of a positioning module, the positioning module is configured to measure a location of at least one location-unrecognized device and a location of a terminal, wherein the at least one location-unrecognized device, the terminal and at least one location-recognized device is located in a certain zone, and wherein the positioning module has coordinate information of the at least one location-recognized device and the positioning module has not coordinate information of the at least one location-unrecognized device.

Abstract: A motor includes a stator on which an armature coil is wound, a rotor disposed inside the stator, a superconducting field coil being wound thereon and, a controller configured to control the motor, in which the controller is configured to control an armature current supplied from an AC source to the armature coil and a field current supplied from a DC source to the field coil, and charge at least a certain ratio of the field coil before starting the motor.

Abstract: Proposed is a bobbin for a superconducting motor by which cooling performance can be obtained and structural stability can be expected. The bobbin for a motor includes a bobbin body on which a superconducting coil is wound and a reinforcement including a reinforced plastic including reinforcing fiber and surrounding a side surface of the bobbin body.

Abstract: An electric motor includes a back yoke provided as an outermost layer of a stator, a stator core including a first teeth portion protruding from the back yoke toward the center portion of the stator and a second teeth portion protruding upwards from the external upper surface of the first teeth portion, a coil winding around the stator core, and a rotor in which a permanent magnet is mounted on the rotor core and which rotates through a magnetic interaction with the stator.

Abstract: Provided is a ReBCO-based high-temperature superconductor composition and a method of preparing the same comprising substituting a part of Gd with Ho, wherein the ReBCO-based high-temperature superconductor is represented by ReBa2Cu3O7-?, in which Re comprises or consists of Gd and Ho. The superconductor may improve the critical current density without a change in the critical temperature.

Abstract: A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

Abstract: A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

Abstract: A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

Abstract: A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; performing a pre-treatment including a first hydrogen annealing on a surface of the substrate; forming a gate dielectric layer over the substrate; performing a post-treatment including a second hydrogen annealing on the substrate including the gate dielectric layer; and forming a gate electrode over the gate dielectric layer.

Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; performing a pre-treatment including a first hydrogen annealing on a surface of the substrate; forming a gate dielectric layer over the substrate; performing a post-treatment including a second hydrogen annealing on the substrate including the gate dielectric layer; and forming a gate electrode over the gate dielectric layer.

Abstract: The present invention discloses methods for manufacturing a capacitor of a semiconductor device employing doped silicon film as an electrode and an oxide film-nitride film-oxide film as a dielectric film. An interlayer insulating film is formed on a semiconductor substrate. A storage electrode is formed consisting of a doped polysilicon on the interlayer insulating film. A first oxide film is formed on the storage electrode that is subjected to a thermal treatment in an atmosphere containing an n-type impurity to implant the impurity into the first oxide film. A nitride film is formed on the first oxide film, whereby the impurity in the first oxide film is diffused into the nitride film. A second oxide film is formed on the nitride film. A plate electrode is then formed on the second oxide film.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming a gate in a cell region and a peripheral region of a substrate, depositing a buffer oxide layer on the gate and the substrate, annealing a resultant structure of the substrate, depositing a nitride spacer layer on the buffer oxide layer, depositing an oxide spacer layer on the nitride spacer layer, forming an oxide spacer at the peripheral region of the substrate, and removing the oxide spacer layer remaining in the cell region. The annealing step is additionally carried out after depositing the buffer oxide layer so as to improve the interfacial surface characteristic and film quality, so that oxide etchant is prevented from penetrating into the silicon substrate during the wet dip process. Unnecessary voids are prevented from being created in the silicon substrate.

Abstract: In fabricating a dielectric layer, a semiconductor substrate which has been washed is provided. A first nitride film is formed by loading the substrate in a first furnace and subjecting the substrate to a first nitride treatment. A first oxide film is formed by unloading the substrate having the first nitride film out of the first furnace and subjecting the substrate to a first nitride treatment by introducing air while the substrate is unloaded. A second nitride film is formed by loading the substrate having the first oxide film in a second furnace and subjecting the substrate to a second nitride treatment. A second oxide film is formed by subjecting the top surface of the second nitride film to a second oxide treatment.

Abstract: A method for forming a device isolation film of a semiconductor device, wherein an annealing process is performed on the oxide film using NH3 prior to the deposition of a liner nitride film and after the deposition of a thermal oxide film on a sidewall of a trench to nitridate the oxide film is disclosed.

Abstract: A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NH3 annealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.

Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: 1. A method for fabricating a semiconductor device, which comprises the steps of: forming a gate line on a semiconductor substrate; forming junction regions in the semiconductor substrate at both sides of the gate line; forming and selectively removing an interlayer insulating film on the substrate to form contact holes exposing the junction regions; forming plugs in the contact holes; and implanting impurity ions into the plugs; and annealing the junction regions.

Abstract: A method for fabricating a capacitor for a semiconductor device is disclosed, which comprises the steps of: forming a storage node electrode on a semiconductor wafer, forming a dielectric layer made of a cyclic silicon nitride layer on the surface of the storage node electrode, and forming an upper electrode on the dielectric layer; lowering the thickness Teff of the dielectric layer and improving leakage current characteristics through use of a cyclic Si3N4 or a cyclic SiOxNy (wherein x falls between 0.1 and 0.9 and y falls between 0.1 and 2), having a large oxidation resistance and high dielectric ratio, as a dielectric.

Abstract: A method for forming of a capacitor wherein an etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film is disclosed. The method comprises the steps of: forming an etching barrier layer on an interlayer insulating film having a storage electrode contact plug therein, the etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film; forming an oxide film on the etching barrier layer; selectively etching the oxide film and the etching barrier layer to form an opening exposing the storage electrode contact plug; depositing a storage electrode layer on the bottom and the inner walls of the opening; and removing the oxide film, whereby forming a storage electrode.

Abstract: A capacitor in a semiconductor device and a method for fabricating the same is disclosed. Disclosed the method for fabricating the capacitor in a semiconductor device comprises the steps of: forming a lower electrode made of doped silicon materials on a semiconductor substrate; depositing a thin silicon nitride layer on the lower electrode; forming a silicon oxynitride layer on the surface of the silicon nitride layer through oxidation of the silicon nitride layer; depositing a dielectric layer on the silicon oxynitride layer; and forming an upper electrode on the dielectric layer.