Patents by Inventor Tae-Joo Hwang

Tae-Joo Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140235017
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Inventors: Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
  • Patent number: 8736035
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Tae-Joo Hwang, Tae-gyeong Chung, Eun-chul Ahn
  • Patent number: 8723315
    Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Joo Lee, Tae-Joo Hwang, Cha-Jea Jo
  • Publication number: 20130200515
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Application
    Filed: March 5, 2013
    Publication date: August 8, 2013
    Inventors: Tae-Joo HWANG, Tae-gyeong Chung, Eun-chul Ahn
  • Patent number: 8421244
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20120223427
    Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Inventors: Jong-Joo LEE, Tae-Joo HWANG, Cha-Jea JO
  • Patent number: 8178969
    Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: May 15, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Joo Lee, Tae-Joo Hwang, Cha-Jea Jo
  • Patent number: 8129221
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20110294260
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Application
    Filed: August 2, 2011
    Publication date: December 1, 2011
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Patent number: 8022555
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20100327439
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Patent number: 7821139
    Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Joo Hwang, Eun-Chul Ahn, Tae-Gyeong Chung
  • Patent number: 7612450
    Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip, and a plurality of conductive balls, e.g., solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip. The adhesive material is applied on an adhesion surface of the dummy board adhered to a joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings. Cheap underfill materials can be selectively used, and a process time for reflow and curing of the adhesive material can be greatly reduced.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: November 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Gi Lee, Tae-Joo Hwang
  • Publication number: 20090230549
    Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jong-Joo Lee, Tae-Joo Hwang, Cha-Jea Jo
  • Patent number: 7560374
    Abstract: A mold for forming a conductive bump, a method of fabricating the mold, and a method of forming a bump on a wafer using the mold are provided. The bump can be formed by employing various materials, the mold can be repeatedly used several times because the mold is not damaged, and due to a high precision, the pitch of the bumps is not limited. The mold for forming a conductive bump comprises a first substrate having a groove to form a bump; a second substrate for vacuum adsorption formed below the first substrate, and having a through-hole in communication with the groove; and a mask layer formed on the first substrate, and used to form the groove.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Joo Hwang
  • Publication number: 20090149016
    Abstract: Provided is a semiconductor device and a method of fabricating the same. The method of fabricating the semiconductor device includes forming a mask pattern having an opening corresponding to an electrode pad formed on a semiconductor substrate; forming a bump by filling the opening with a conductive first material; forming a sidewall film on sidewalls of the bump using a second material; forming a connection member between an upper surface of the bump and a wire substrate using a conductive third material in order to electrically connect the bump and the wire substrate; and forming an underfill resin between the wire substrate and the semiconductor substrate, wherein a wetting angle between the second material and the third material is greater than that between the first material and the third material.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 11, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo PARK, Tae-Joo HWANG, Nam-Seog KIM
  • Publication number: 20080277800
    Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
    Type: Application
    Filed: May 7, 2008
    Publication date: November 13, 2008
    Inventors: Tae-Joo Hwang, Tae-Gyeong Chung, Eun-Chul Ahn
  • Publication number: 20080268579
    Abstract: A semiconductor chip package capable of improving reliability at a chip interconnection portion and improving reliability in a solder joint by reducing thermal and mechanical stresses at an external portion of the package including a solder ball land, and a method of fabricating the package are provided. The method of fabricating a semiconductor chip package includes providing a substrate; forming a first underfill on a first portion of the substrate; forming a second underfill at a chip interconnection portion of the substrate; and mounting a semiconductor chip on the chip interconnection portion using conductive bumps. In the method, the second underfill is formed of a material having a modulus higher than the first underfill.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 30, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Jung YU, Mu-Seob SHIN, Tae-Joo HWANG, Tae-Gyeong CHUNG, Eun-Chul AHN
  • Publication number: 20080258288
    Abstract: In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips and connected to the substrate via a bump disposed between the lower chips. As no wire loops are formed, there is no increase in the height of the stack package, and the electrical path is shortened, thereby improving the electric performance of the stack package. Also, the semiconductor device stack package has a flip chip structure, and thus a plurality of semiconductor chips can be stacked in various manners.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 23, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-woo Park, Cha-je Jo, Eun-chul Ahn, Tae-joo Hwang, Hae-jung Yu, Chan Park
  • Publication number: 20080122084
    Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 29, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joo HWANG, Eun-Chul AHN, Tae-Gyeong CHUNG