Abstract: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

Abstract: A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage level that is reinforced as compared with a voltage level of the driving voltage. The load driver drives a load based on the driving voltage and the driving signal.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided. The precharge control circuit may be embodied as a delay circuit unit which receives and delays a precharge enable signal for a predetermined delay time; a NAND gate which receives the precharge enable signal and the output of the delay circuit; and an inverter which inverts the output of the NAND gate. The precharge control circuit may enable the word lines before disabling the precharge signal.

Abstract: An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising a ground voltage by a threshold voltage of a transistor. Due to the use of PMOS and NMOS transistors of diode types connected between the power supply voltage and the virtual power supply voltage and the use of NMOS and PMOS transistors of diode types connected between the ground voltage and the virtual ground voltage, a virtual power supply voltage level and a virtual ground voltage level that are stable even against various PVT variations are provided, so that low-leakage current characteristics are stable.

Abstract: Provided are a sense amplifier driver and a semiconductor device comprising the same. The sense amplifier driver outputting an enable signal for enabling a sense amplifier includes a first inverter, which receives an input signal and outputs an output signal swung between a ground voltage and a control voltage that is determined by the amount of an off-current flowing through at least one transistor existing in an inactive memory block, and a second inverter, which receives the output signal of the first inverter and delays and buffers the output signal of the first inverter by a period of time inversely proportional to a level of the control voltage. A point of time when the enable signal is activated varies according to a level of the control voltage. The semiconductor device detects data in response to the enable signal.

Abstract: Provided are a sense amplifier driver and a semiconductor device comprising the same. The sense amplifier driver outputting an enable signal for enabling a sense amplifier includes a first inverter, which receives an input signal and outputs an output signal swung between a ground voltage and a control voltage that is determined by the amount of an off-current flowing through at least one transistor existing in an inactive memory block, and a second inverter, which receives the output signal of the first inverter and delays and buffers the output signal of the first inverter by a period of time inversely proportional to a level of the control voltage. A point of time when the enable signal is activated varies according to a level of the control voltage. The semiconductor device detects data in response to the enable signal.

Abstract: A semiconductor device having a sense amplifier driver with a capacitor affected by off current is provided. The sense amplifier driver, which receives a clock signal and generates a sense amplifier enable signal by buffering the clock signal, includes a plurality of inverters connected in series and at least one capacitor. A PMOS transistor of at least a first inverter of the plurality of inverters is connected between a dummy bit line, in which voltage drop by the off current is generated, and the output terminal of the first inverter and the at least one capacitor is connected between the dummy bit line and the output terminal of a second inverter which inverts an output signal of the first inverter. Therefore, the capacitance of the at least one capacitor is determined by voltage of the dummy bit line. Therefore, since the voltage drop of the dummy bit line is larger when the magnitude of the off current is larger, the capacitance of the at least one capacitor is larger.

Abstract: Provided are a sense amplifier driver and a semiconductor device comprising the same. The sense amplifier driver outputting an enable signal for enabling a sense amplifier includes a first inverter, which receives an input signal and outputs an output signal swung between a ground voltage and a control voltage that is determined by the amount of an off-current flowing through at least one transistor existing in an inactive memory block, and a second inverter, which receives the output signal of the first inverter and delays and buffers the output signal of the first inverter by a period of time inversely proportional to a level of the control voltage. A point of time when the enable signal is activated varies according to a level of the control voltage. The semiconductor device detects data in response to the enable signal.

Abstract: Provided are a semiconductor device having a sense amplifier driver and a method of generating a sense amplifier enable signal for enabling a sense amplifier. The semiconductor device includes a sense amplifier, which is comprised of a plurality of inverters which are connected in series, a power supply circuit, and a discharge circuit. In this semiconductor device, an enabling timing of the sense amplifier enable signal is controlled by delaying a time taken to evaluate a first dummy bit line from a power supply voltage to a ground voltage using parasitic capacitance between the first dummy bit line and a first complementary dummy bit line. The method of generating the sense amplifier enable signal is performed using the above-described sense amplifier.

Abstract: An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising a ground voltage by a threshold voltage of a transistor. Due to the use of PMOS and NMOS transistors of diode types connected between the power supply voltage and the virtual power supply voltage and the use of NMOS and PMOS transistors of diode types connected between the ground voltage and the virtual ground voltage, a virtual power supply voltage level and a virtual ground voltage level that are stable even against various PVT variations are provided, so that low-leakage current characteristics are stable.

Abstract: A semiconductor memory device, that reduces load capacitance of write-only bit lines, may include: a first bit cell array block, in which bit cells thereof are defined by intersections of first bit lines and first word lines, the first bit lines being arranged as pairs of first signal lines and second signal lines, respectively; a second bit cell array block, in which bit cells thereof are defined by intersections of second bit lines and second word lines, the second bit lines being arranged as pairs of third signal lines and the second signal lines; respectively; a block division circuit operable to generate and output block division control signals; and a write bit line divider circuit operable to either open-circuit or connect together the first signal lines and the third signal lines, respectively, according to the block division control signals.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: Provided are a semiconductor device having a sense amplifier driver and a method of generating a sense amplifier enable signal for enabling a sense amplifier. The semiconductor device includes a sense amplifier, which is comprised of a plurality of inverters which are connected in series, a power supply circuit, and a discharge circuit. In this semiconductor device, an enabling timing of the sense amplifier enable signal is controlled by delaying a time taken to evaluate a first dummy bit line from a power supply voltage to a ground voltage using parasitic capacitance between the first dummy bit line and a first complementary dummy bit line. The method of generating the sense amplifier enable signal is performed using the above-described sense amplifier.

Abstract: A semiconductor device having a sense amplifier driver with a capacitor affected by off current is provided. The sense amplifier driver, which receives a clock signal and generates a sense amplifier enable signal by buffering the clock signal, includes a plurality of inverters connected in series and at least one capacitor. A PMOS transistor of at least a first inverter of the plurality of inverters is connected between a dummy bit line, in which voltage drop by the off current is generated, and the output terminal of the first inverter and the at least one capacitor is connected between the dummy bit line and the output terminal of a second inverter which inverts an output signal of the first inverter. Therefore, the capacitance of the at least one capacitor is determined by voltage of the dummy bit line. Therefore, since the voltage drop of the dummy bit line is larger when the magnitude of the off current is larger, the capacitance of the at least one capacitor is larger.

Abstract: The present invention includes a dual port static memory cell and a semiconductor memory device having the same, the dual port static memory cell comprising a first transmission gate having a gate connected to a word line and connected between a bit line and a first node, a second transmission gate having a gate connected to the word line and connected between a complementary bit line and a second node, a latch connected between the first node and the second node, and a PMOS transistor having a gate connected to a scan control line and connected between the second node and a scan bit line.