Abstract: Provided are a sense amplifier driver and a semiconductor device comprising the same. The sense amplifier driver outputting an enable signal for enabling a sense amplifier includes a first inverter, which receives an input signal and outputs an output signal swung between a ground voltage and a control voltage that is determined by the amount of an off-current flowing through at least one transistor existing in an inactive memory block, and a second inverter, which receives the output signal of the first inverter and delays and buffers the output signal of the first inverter by a period of time inversely proportional to a level of the control voltage. A point of time when the enable signal is activated varies according to a level of the control voltage. The semiconductor device detects data in response to the enable signal.

Abstract: A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided. The precharge control circuit may be embodied as a delay circuit unit which receives and delays a precharge enable signal for a predetermined delay time; a NAND gate which receives the precharge enable signal and the output of the delay circuit; and an inverter which inverts the output of the NAND gate. The precharge control circuit may enable the word lines before disabling the precharge signal.

Abstract: A semiconductor memory device, that reduces load capacitance of write-only bit lines, may include: a first bit cell array block, in which bit cells thereof are defined by intersections of first bit lines and first word lines, the first bit lines being arranged as pairs of first signal lines and second signal lines, respectively; a second bit cell array block, in which bit cells thereof are defined by intersections of second bit lines and second word lines, the second bit lines being arranged as pairs of third signal lines and the second signal lines; respectively; a block division circuit operable to generate and output block division control signals; and a write bit line divider circuit operable to either open-circuit or connect together the first signal lines and the third signal lines, respectively, according to the block division control signals.

Abstract: A sense amplifier driver circuit for generating a sense amplifier enable signal that enables a sense amplifier that drives a bit line coupled to a pass transistor of a memory cell includes an inverter that generates the sense amplifier enable signal, the inverter comprising a plurality of series-connected MOS transistors of the same conductivity type as the pass transistor. The plurality of series-connected MOS transistors may have an overall channel width/length ratio that is substantially the same as a channel width/length ratio of the pass transistor. The aggregate length of the series-connected transistors may be substantially the same as a length of the pass transistor, and widths of the series-connected transistors may be different from a width of the pass transistor.

Abstract: The present invention includes a dual port static memory cell and a semiconductor memory device having the same, the dual port static memory cell comprising a first transmission gate having a gate connected to a word line and connected between a bit line and a first node, a second transmission gate having a gate connected to the word line and connected between a complementary bit line and a second node, a latch connected between the first node and the second node, and a PMOS transistor having a gate connected to a scan control line and connected between the second node and a scan bit line.

Abstract: Disclosed is a semiconductor memory device and a data read method thereof. The semiconductor memory device comprises a memory cell array comprising a plurality of sub-arrays, said sub-arrays comprising a plurality of memory cells and repeaters, wherein each of said memory cells is connected to a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines, and a corresponding pair of write bitlines, and wherein each of said repeaters is connected to said corresponding pair of read bitlines of each said memory cell and a corresponding pair of common main read bitlines so as to transmit read data from said corresponding pair of read bitlines to said corresponding pair of common main read bitlines in response to an applied enable control signal.

Abstract: A sense amplifier driver circuit for generating a sense amplifier enable signal that enables a sense amplifier that drives a bit line coupled to a pass transistor of a memory cell includes an inverter that generates the sense amplifier enable signal, the inverter comprising a plurality of series-connected MOS transistors of the same conductivity type as the pass transistor. The plurality of series-connected MOS transistors may have an overall channel width/length ratio that is substantially the same as a channel width/length ratio of the pass transistor. The aggregate length of the series-connected transistors may be substantially the same as a length of the pass transistor, and widths of the series-connected transistors may be different from a width of the pass transistor.

Abstract: A CMOS cross-coupled sense amplifier circuit that detects and amplifies data of memory cells is disclosed. The sense amplifier having a favorable sense margin even if a mismatch occurs in transistors constructing the sense amplifier in the fabricating process. The sense amplifier includes voltage control transistors that control the voltage between drain and source of the NMOS transistors in the inverters connected in a latch type between output nodes at an identical phase during a pre-charge step and during an initial operation step. The channels of the voltage control transistors are connected between the drain and source of the NMOS transistors in the inverters for being controlled by a sense amplifier signal.

Abstract: A CMOS cross-coupled sense amplifier circuit that detects and amplifies data of memory cells is disclosed. The sense amplifier having a favorable sense margin even if a mismatch occurs in transistors constructing the sense amplifier in the fabricating process. The sense amplifier includes voltage control transistors that control the voltage between drain and source of the NMOS transistors in the inverters connected in a latch type between output nodes at an identical phase during a pre-charge step and during an initial operation step. The channels of the voltage control transistors are connected between the drain and source of the NMOS transistors in the inverters for being controlled by a sense amplifier signal.

Abstract: Disclosed is a semiconductor memory device and a data read method thereof. The semiconductor memory device comprises a memory cell array comprising a plurality of sub-arrays, said sub-arrays comprising a plurality of memory cells and repeaters, wherein each of said memory cells is connected to a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines, and a corresponding pair of write bitlines, and wherein each of said repeaters is connected to said corresponding pair of read bitlines of each said memory cell and a corresponding pair of common main read bitlines so as to transmit read data from said corresponding pair of read bitlines to said corresponding pair of common main read bitlines in response to an applied enable control signal.