Abstract: A method of manufacturing a multilayer metal plate by electroplating includes a first forming operation of forming one of a first metal layer and a second metal layer on a substrate by electroplating, wherein the second metal layer is less recrystallized than the first metal layer, the second metal layer is comprised of nanometer-size grains, and the second metal layer has a higher level of tensile strength than the first metal layer; and a second forming operation of forming, by electroplating, a third metal layer not formed in the first forming operation on a surface of one of the first metal layer and the second metal layer formed in the first forming operation.

Abstract: An electronic device includes an internal mode control circuit suitable for generating a burst control signal, a blocking control signal and an internal voltage control signal based on a refresh cycle when an internal mode is performed in a self-refresh operation, a refresh control circuit suitable for generating a refresh signal for performing a refresh operation every refresh cycle when the self-refresh operation is performed, generating the refresh signal every set cycle based on the burst control signal when the internal mode is performed, and blocking the generation of the refresh signal based on the blocking control signal, and an internal voltage generation circuit suitable for adjusting a level of an internal voltage for the refresh operation based on the internal voltage control signal.

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Abstract: An electronic device includes an internal mode control circuit suitable for generating a burst control signal, a blocking control signal and an internal voltage control signal based on a refresh cycle when an internal mode is performed in a self-refresh operation, a refresh control circuit suitable for generating a refresh signal for performing a refresh operation every refresh cycle when the self-refresh operation is performed, generating the refresh signal every set cycle based on the burst control signal when the internal mode is performed, and blocking the generation of the refresh signal based on the blocking control signal, and an internal voltage generation circuit suitable for adjusting a level of an internal voltage for the refresh operation based on the internal voltage control signal.

Abstract: A semiconductor device may be provided. The semiconductor device may include a latch comparison circuit configured for generating a latched address by latching a pattern signal inputted through an address, and generate a comparison signal by comparing a pattern signal inputted through the address and the latched address. The semiconductor device may include a failure flag generation circuit configured for generating a failure flag signal based on the comparison signal.

Abstract: A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. Further included is an output circuit suitable for outputting the fuse data in response to the third internal command.

Abstract: A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. Further included is an output circuit suitable for outputting the fuse data in response to the third internal command.

Abstract: A boot-up control circuit may be provided. The boot-up control circuit may include a fuse array including a one or more normal fuses and one or more dummy fuses. The boot-up control circuit may include a fuse array controller configured to determine whether or not to start a normal boot-up operation for the one or more normal fuses according to a comparison result between expected data and test fuse data output from the one or more dummy fuses through a test boot-up operation.

Abstract: A semiconductor device may be provided. The semiconductor device may include a latch comparison circuit configured for generating a latched address by latching a pattern signal inputted through an address, and generate a comparison signal by comparing a pattern signal inputted through the address and the latched address. The semiconductor device may include a failure flag generation circuit configured for generating a failure flag signal based on the comparison signal.

Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.

Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.

Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.

Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.

Abstract: The semiconductor device includes a latch pulse generator and a data latch unit. The latch pulse generator generates a test section signal in response to a test pulse signal. Further, the latch pulse generator generates a first latch pulse signal in response to the test pulse signal and the test section signal. The data latch unit latches a selection data in response to the first latch pulse signal to generate a fuse data for programming a fuse array.

Abstract: The semiconductor system includes a controller and a semiconductor device. The controller outputs commands and receives an output datum to discriminate whether at least one of a plurality of fuse cells abnormally operates. The semiconductor device compares logic levels of a plurality of fuse data generated from the plurality of fuse cells with each other, thereby generating a flag signal enabled when at least one of the logic levels of the plurality of fuse data is different from the other logic levels while a boot-up operation is executed according to a combination of the commands. In addition, the semiconductor device outputs the flag signal as the output datum while a read operation is executed according to a combination of the commands.

Abstract: The semiconductor system includes a controller and a semiconductor device. The controller outputs commands and receives an output datum to discriminate whether at least one of a plurality of fuse cells abnormally operates. The semiconductor device compares logic levels of a plurality of fuse data generated from the plurality of fuse cells with each other, thereby generating a flag signal enabled when at least one of the logic levels of the plurality of fuse data is different from the other logic levels while a boot-up operation is executed according to a combination of the commands. In addition, the semiconductor device outputs the flag signal as the output datum while a read operation is executed according to a combination of the commands.

Abstract: A semiconductor device including a first latch unit suitable for storing a first address of a first memory cell tested in a first cell array block, a second latch unit suitable for storing a second address of a second memory cell tested in a second cell array block, a first selector suitable for receiving a first selection signal or a second selection signal to output any one of the first address and the second address as a selected address, and a program controller suitable for determining whether the selected address has to be stored in a fuse array and to control an operation for programming the fuse array.

Abstract: The semiconductor device includes a latch pulse generator and a data latch unit. The latch pulse generator generates a test section signal in response to a test pulse signal. Further, the latch pulse generator generates a first latch pulse signal in response to the test pulse signal and the test section signal. The data latch unit latches a selection data in response to the first latch pulse signal to generate a fuse data for programming a fuse array.

Abstract: A semiconductor device including a first latch unit suitable for storing a first address of a first memory cell tested in a first cell array block, a second latch unit suitable for storing a second address of a second memory cell tested in a second cell array block, a first selector suitable for receiving a first selection signal or a second selection signal to output any one of the first address and the second address as a selected address, and a program controller suitable for determining whether the selected address has to be stored in a fuse array and to control an operation for programming the fuse array.