Abstract: A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and has a contact hole partially exposing the doped poly-Si1-xGex layer. A metal contact plug is in the contact hole and an interconnection layer is disposed on the interlayer insulating layer and connected to the metal contact plug. Related interconnection structures and fabrication methods are also disclosed.

Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.

Abstract: An example embodiment of a non-volatile memory device and an example embodiment of a method of fabricating the same are provided. The non-volatile memory devices includes a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a blocking insulation layer including at least one nano dot on the charge storage layer, and a control gate electrode on the blocking insulation layer.

Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

Abstract: A flash memory device including a hybrid structure charge trap layer and a related method of manufacture are disclosed. The charge trap layer includes at least one hybrid trap layer including a first trap layer formed from a first material having a first band gap energy, and a plurality of nano dots separated from each other such that each nano dot is at least partially encircled by the first trap layer, the plurality of nano dots being formed from a second material having a second band gap energy lower than the first band gap energy.

Abstract: A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Abstract: A photoresist resin composition comprises about 10 to about 35% by weight of an acryl-based copolymer, about 5 to about 10% by weight of a quinone diazide compound, about 55 to about 80% by weight of a solvent, and about 0.01 to about 0.5% by weight of a silane-based surfactant where the weights of each of the acryl-based copolymer, quinone diazide compound, solvent, and silane-based surfactant are based on the total weight of acryl-based copolymer, quinone diazide compound, solvent, and silane-based surfactant. An overcoating layer formed using the photoresist resin composition has improved flatness, and thus defects on a display screen may be prevented and/or reduced.

Abstract: A display includes; a substrate including a display region and a peripheral region, a common line portion provided in the peripheral region of the substrate, and the common line portion includes a common line and a common line protruding portion which extends away from and is wider than the common line, and a dummy pattern portion which partially overlaps a boundary region between the common line and the common line protruding portion.

Abstract: A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and has a contact hole partially exposing the doped poly-Si1-xGex layer. A metal contact plug is in the contact hole and an interconnection layer is disposed on the interlayer insulating layer and connected to the metal contact plug. Related interconnection structures and fabrication methods are also disclosed.

Abstract: Disclosed herein is a method and apparatus for managing ring-back sounds in a subscriber-based ring-back sound service. The method includes the first step of storing common ring-back sounds and reporting details of use of the common ring-back sounds, the second step of storing individual ring-back sounds and reporting details of use of the individual ring-back sounds, and the third step of statistically compiling the reported details of use and determining whether to maintain storage of the ring-back sounds based up the statistically complied details. A method and apparatus for presenting and changing ring-back sounds based upon the ring-back sound managing method and apparatus are provided.

Abstract: A method for controlling routing information for intellectual peripherals (IPs) in a subscriber-based ring-back-tone service. The routing information to be routed to IPs (50) corresponding to subscribers is classified on a subscriber telephone number-by-number basis, a subscriber telephone office number-by-number basis, a subscriber telephone office number group-by-group basis or a subscriber's major activity area-by-area basis according to a selection. The classified routing information is set and registered in a home location register (HLR) (10). When the HLR (10) receives a location registration request message from a terminal of an arbitrary subscriber, a corresponding routing information item to be routed to an IP (50) corresponding to the subscriber's terminal among the classified, set and registered routing information is contained within a response message to the location registration request message, and the response message is provided to a terminating mobile switching center (T MSC) (32).

Abstract: A photoresist resin composition comprises about 10 to about 35% by weight of an acryl-based copolymer, about 5 to about 10% by weight of a quinone diazide compound, about 55 to about 80% by weight of a solvent, and about 0.01 to about 0.5% by weight of a silane-based surfactant where the weights of each of the acryl-based copolymer, quinone diazide compound, solvent, and silane-based surfactant are based on the total weight of acryl-based copolymer, quinone diazide compound, solvent, and silane-based surfactant. An overcoating layer formed using the photoresist resin composition has improved flatness, and thus defects on a display screen may be prevented and/or reduced.

Abstract: Provided herein are methods of forming a silicon dioxide layer on a substrate using an atomic layer deposition (ALD) method that include supplying a Si precursor to the substrate and forming on the substrate a Si layer including at least one Si atomic layer; and (b) supplying an oxygen radical to the Si layer to replace at least one Si—Si bond within the Si layer with a Si—O bond, thereby oxidizing the Si layer, to form a silicon dioxide layer on the substrate.

Abstract: In non-volatile memory devices and methods of manufacturing the non-volatile memory devices, a barrier layer having an upper portion of silicon nitride and a lower portion of silicon oxide is formed on a substrate by providing a silicon oxide layer on the substrate and performing a radical nitridation process on an upper portion of the silicon oxide layer. A trapping layer including silicon nitride is formed on the barrier layer. A blocking layer and a gate electrode layer are subsequently formed on the trapping layer. The gate electrode layer, the blocking layer, the trapping layer and the barrier layer are then partially etched to provide a gate structure.

Abstract: A method of forming a silicon layer on a substrate includes providing a silicon source gas to form an amorphous silicon layer on a substrate and providing a dopant source gas to adsorb dopants onto the amorphous silicon layer to form a dopant layer on a surface of the amorphous silicon layer. Related floating gates are also disclosed.

Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.

Abstract: A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The single electrode is formed on the charge trap insulator, comprises a P-type impurity receptive semiconductor material, and is doped with P-type impurities.

Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

Abstract: A method for controlling routing information for intellectual peripherals (IPs) in a subscriber-based ring-back-tone service. The routing information to be routed to IPs (50) corresponding to subscribers is classified on a subscriber telephone number-by-number basis, a subscriber telephone office number-by-number basis, a subscriber telephone office number group-by-group basis or a subscriber's major activity area-by-area basis according to a selection. The classified routing information is set and registered in a home location register (HLR) (10). When the HLR (10) receives a location registration request message from a terminal of an arbitrary subscriber, a corresponding routing information item to be routed to an IP (50) corresponding to the subscriber's terminal among the classified, set and registered routing information is contained within a response message to the location registration request message, and the response message is provided to a terminating mobile switching center (T MSC) (32).

Abstract: A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.