Abstract: A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure is disclosed. The vertical field effect transistor elements (1702, 1704, 1706, 1708, 1720, 1724) are made of III-V semiconductor compound grown on a germanium substrate (1726).

Abstract: The present invention comprises a method and apparatus for increasing doping uniformity in semiconductor devices produced in a flow flange reactor. One aspect of the present invention involves dividing the flow flange (12) of the reactor into a plurality of sections (14, 16, 18). Each section (14, 16, 18) is then subdivided into a plurality of subsections (52, 54, 56) including a first subsection (52), a second subsection (54) and a third subsection (56). A group III gas may then be dispersed in the first subsection (52) of at least one section (18). A group V gas may then be dispersed in a second subsection (54) of that section, while a dopant gas may also be dispersed in a third subsection (56) of that section (18).

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.

Abstract: A nail file apparatus is provided which consists of a housing with a handle extending from a rear portion of the housing. A nail file has a tip portion, a heel portion and ridges therebetween. A mechanism within said housing is for causing a reciprocating movement. A structure is for coupling the heel portion of the nail file to the reciprocating movement mechanism at a front portion of the housing. A person can grip the handle and activate the reciprocating movement mechanism, to operate the nail file extending therefrom. The ridges will automatically smooth, polish and shape the fingernails.

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.

Abstract: The use of trimethylarsine in place of tertiary butyl arsine for low pressure organometallic vapor phase epitaxy of GaAs:C to enhance the carbon doping efficiency of CCl.sub.4. The hole concentration is three times higher with trimethylarsine then with tertiary butyl arsine in the layer grown under similar conditions. As a result, higher growth temperatures can be used with trimethyl arsine, yielding more stable carbon doping. Annealing at 650.degree. C. for 5 minutes does not degrade the trimethyl arsine-grown layers while the tertiary butyl arsine-grown layer shows decreases in both hole concentration and mobility. Also a high level of hydrogen atoms is detected in tertiary butyl arsine-grown GaAs:C. The hydrogen level is about 30 times lower in the layers grown with trimethyl arsine. The reduced hydrogen concentration is an added advantage of using trimethyl arsine since hydrogen is known to neutralize acceptors in GaAs to reduce the carrier concentrations.

Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

Abstract: In one form of the invention, a method is disclosed for growing CaF.sub.2 on a silicon surface, comprising the steps of maintaining the silicon surface at a first temperature below approximately 500.degree. C., starting a deposition of CaF.sub.2 on the silicon surface, stopping the deposition, and then annealing the CaF.sub.2 in forming gas at a temperature below 600.degree. C.