Patents by Inventor Tae Seok Oh

Tae Seok Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943939
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 9, 2021
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 10523302
    Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 31, 2019
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Inkyu Lee, Jong-Ho Oh, Bong-Jin Kim, Tae-Yeong Kim, Min-Ki Ahn, Tae-Seok Oh, Seok-Ju Jang
  • Publication number: 20190189668
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventors: BYUNG-JUN PARK, CHANG-ROK MOON, SEUNG-HUN SHIN, SEONG-HO OH, TAE-SEOK OH, JUNE-TAEG LEE
  • Patent number: 10229949
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Publication number: 20180262255
    Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.
    Type: Application
    Filed: September 23, 2016
    Publication date: September 13, 2018
    Inventors: Inkyu LEE, Jong-Ho OH, Bong-Jin KIM, Tae-Yeong KIM, Min-Ki AHN, Tae-Seok OH, Seok-Ju JANG
  • Patent number: 10063260
    Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-generation (4G) communication system such as long term evolution (LTE). Disclosed are an apparatus and a method for a permutation of a block code in a wireless communication system. A method of operating a transmitting node in a wireless communication system includes: determining a permutation matrix according to a block code scheme; generating symbols corresponding to a plurality of antennas based on the block code scheme and the permutation matrix; and transmitting the symbols to a receiving node through the plurality of antennas. The permutation matrix is determined based on a number of blocks and an arrangement structure of the plurality of antennas, and the number of blocks comprises a number of sub-blocks within a code block corresponding to the permutation matrix.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 28, 2018
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Chanhong Kim, Inkyu Lee, Hoon Lee, Ji Hwan Moon, Tae Seok Oh, Seok Ju Jang
  • Patent number: 9894301
    Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Gu Jin, Min Ho Kim, Tae Chan Kim, Dong Ki Min, Sang Chul Sul, Tae Seok Oh, Kwang Hyun Lee, Tae Yon Lee, Ju Hwan Jung
  • Publication number: 20180006666
    Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-generation (4G) communication system such as long term evolution (LTE). Disclosed are an apparatus and a method for a permutation of a block code in a wireless communication system. A method of operating a transmitting node in a wireless communication system includes: determining a permutation matrix according to a block code scheme; generating symbols corresponding to a plurality of antennas based on the block code scheme and the permutation matrix; and transmitting the symbols to a receiving node through the plurality of antennas. The permutation matrix is determined based on a number of blocks and an arrangement structure of the plurality of antennas, and the number of blocks comprises a number of sub-blocks within a code block corresponding to the permutation matrix.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 4, 2018
    Inventors: Chanhong Kim, Inkyu Lee, Hoon Lee, Ji Hwan Moon, Tae Seok Oh, Seok Ju Jang
  • Publication number: 20170287967
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: BYUNG-JUN PARK, CHANG-ROK MOON, SEUNG-HUN SHIN, SEONG-HO OH, TAE-SEOK OH, JUNE-TAEG LEE
  • Patent number: 9728572
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Publication number: 20160365374
    Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 15, 2016
    Inventors: Byung-Jun PARK, Seung-Hun SHIN, Chang-Rok MOON, Tae-Seok OH, June-Taeg LEE
  • Patent number: 9455284
    Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Jun Park, Seung-Hun Shin, Chang-Rok Moon, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 9432604
    Abstract: An image sensor chip includes a first wafer and a second wafer. The first wafer includes an image sensor having a plurality of sub-pixels, each of which is configured to detect at least one photon and output a sub-pixel signal according to a result of the detection. The image processor is configured to process sub-pixel signals for each sub-pixel and generate image data. The first wafer and the second wafer are formed in a wafer stack structure.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Chan Kim, Min Ho Kim, Dong Ki Min, Sang Chul Sul, Tae Seok Oh, Kwang Hyun Lee, Tae Yon Lee, Jung Hoon Jung, Young Gu Jin
  • Patent number: 9357142
    Abstract: An image sensor includes a pixel array and a row driver block. The pixel array includes a plurality of subpixel groups, each including a plurality of subpixels. Each of the plurality of subpixels is configured to generate a subpixel signal corresponding to photocharge accumulated in response to a photon. The row driver block is configured to generate a first control signal to control the subpixels included in each of the plurality of subpixel groups to accumulate the photocharge in parallel from a first time point to a second time point.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 31, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Chan Kim, Min Ho Kim, Dong Ki Min, Sang Chul Sul, Tae Seok Oh, Kwang Hyun Lee, Tae Yon Lee, Jung Hoon Jung, Young Gu Jin
  • Publication number: 20160028977
    Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 28, 2016
    Inventors: Young Gu JIN, Min Ho Kim, Tae Chan Kim, Dong Ki Min, Sang Chul Sul, Tae Seok Oh, Kwang Hyun Lee, Tae Yon Lee, Ju Hwan Jung
  • Patent number: 9177987
    Abstract: A binary complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array and a readout circuit. The pixel array includes at least one pixel having a plurality of sub-pixels. The readout circuit is configured to quantize a pixel signal output from the pixel using a reference signal. The pixel signal corresponds to sub-pixel signals output from sub-pixels, from among the plurality of sub-pixels, activated in response to incident light.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Yon Lee, Ju Hwan Jung, Seok Yong Hong, Tae-Chan Kim, Dong Ki Min, Yoon Dong Park, Sang-Chul Sul, Tae-Seok Oh, Je Il Ryu, Kwang-Hyun Lee, Young-Gu Jin
  • Publication number: 20150311241
    Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.
    Type: Application
    Filed: January 22, 2015
    Publication date: October 29, 2015
    Inventors: Byung-Jun PARK, Seung-Hun SHIN, Chang-Rok MOON, Tae-Seok OH, June-Taeg LEE
  • Patent number: 9165974
    Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-kwan Kim, Doo-won Kwon, Jeong-ki Kim, Wook-hwan Kim, Byung-jun Park, Seung-hun Shin, June-taeg Lee, Ha-kyu Choi, Tae-seok Oh
  • Publication number: 20150221695
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Application
    Filed: December 5, 2014
    Publication date: August 6, 2015
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Publication number: 20150076649
    Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventors: Sung-kwan KIM, Doo-Won Kwon, Jeong-ki Kim, Wook-hwan Kim, Byung-jun Park, Seung-hun Shin, June-taeg Lee, Ha-kyu Choi, Tae-Seok Oh