Patents by Inventor Tae Seok Oh

Tae Seok Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12128736
    Abstract: A heat pump system for a vehicle includes a valve, an electrical component cooling device, a battery cooling device, an indoor heating device, an indoor cooling device, a centralized energy device, and a chiller to improve heating efficiency by regulating a temperature of a battery module by use of one chiller in which a cooler and a refrigerant exchange heat, recovers various heat sources in a heating mode of the vehicle and utilizes the recovered heat sources for indoor heating.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: October 29, 2024
    Assignees: Hyundai Motor Company, Kia Corporation
    Inventors: Wan Je Cho, Dong Seok Oh, Namho Park, Seung Ho Lee, Seong-Bin Jeong, Tae Hee Kim, Jae-Eun Jeong, Jeawan Kim, Hyunjae Lee, Man Hee Park, Jae Yeon Kim, Yeonho Kim
  • Patent number: 12121375
    Abstract: A computed tomography (CT) apparatus includes a gantry including a rotation device which has a ring shape and is rotatable about an axis of rotation, a plurality of light sources configured to emit X-rays to a subject, at least one detector provided on the rotation device and configured to detect X-rays passing through the subject, and one or more processors. The at least one processors are configured to rotate the rotation device in a first rotation direction by an angle of rotation determined based on a total number of the plurality of light sources, emit X-rays to the subject and detect X-rays passing through the subject during the rotation of the rotation device in the first rotation direction, and rotate the rotation device by the determined rotation angle in a second rotation direction.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: October 22, 2024
    Assignee: KOH YOUNG TECHNOLOGY INC.
    Inventors: Young Jun Roh, Min Sik Shin, Sung Hoon Kang, Tae Seok Oh
  • Patent number: 12101477
    Abstract: Disclosed herein are a video processing method, apparatus and storage medium using the resolution of a reference picture. Filtering is performed based on resolutions of reference pictures of blocks forming a boundary. The resolutions of the reference pictures may define filtering. Depending on whether the resolutions of the reference pictures are different from each other, one or more filter selection parameters for filtering may be determined or updated. Further, based on whether the resolutions of the reference pictures are different from each other, the boundary strength of the filter may be determined. Because filtering is defined using the resolutions of reference pictures, performance of encoding and/or decoding may be improved.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: September 24, 2024
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KWANGWOON UNIVERSITY INDUSTRY-ACADEMIC COLLABORATION FOUNDATION
    Inventors: Seoung-Jun Oh, Woong Lim, Gun Bang, Tae-Jin Lee, Dong-Gyu Sim, Jun-Taek Park, Min-Hun Lee, Jong-Seok Lee
  • Patent number: 12097385
    Abstract: A lung phantom unit for radiotherapy according to an embodiment of the present disclosure may arrange, at a location not affected by a magnetic field, a phantom driving cylinder and a driving device which may move a lung mimic and a tumor mimic in a lung simulation block. The lung phantom unit may be used for general purpose even as a phantom for MRI-based and CT image-based radiotherapy. Since lung and tumor motions are implemented by air injection, it may be possible to precisely measure the motion and volume change of a lung according to subtle changes in air pressure so that customized radiotherapy suitable for a patient having various breathing patterns is possible.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 24, 2024
    Assignee: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Young Nam Kang, Tae Geon Oh, Yun Ji Seol, Na Young An, Jae Hyeon Lee, Chul Seung Kay, Jin Sol Shin, Jin Ho Hwang, Hun Joo Shin, Myung Ho Kim, Hong Seok Jang
  • Publication number: 20240199458
    Abstract: Disclosed is a carrier, of which biofilms are appropriately adjustable in thickness. In accordance with an aspect of the present disclosure, there is provided a complex carrier included in one component of a sewage treatment apparatus to allow microorganisms to be attached and grown therein. The complex carrier includes a first carrier having a plural spaces for microorganisms to be attached therein to allow microorganisms to be attached and grown therein; and a second carrier having a structure capable of penetrating or passing through the spaces of the first carrier to adjust the thickness of biofilms formed in the spaces of the first carrier.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 20, 2024
    Applicant: BKT CO., LTD.
    Inventors: Min Ki JUNG, Tae Seok OH, Yun Su LIM, Dae Hwan RHU, Ghimire UMESH
  • Patent number: 11969272
    Abstract: A computed tomography (CT) apparatus according to various embodiments may include a gantry including a first rotation device, a second rotation device and a third rotation device which have a ring shape, share an axis of rotation, and are rotatable independently of one another, a plurality of first light sources provided on the first rotation device at regular intervals and configured to emit X-rays to a subject, a plurality of second light sources provided on the second rotation device at regular intervals and configured to emit X-rays to the subject, a detector provided on a region of the third rotation device and configured to detect X-rays passing through the subject, and one or more processors.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 30, 2024
    Assignee: KOH YOUNG TECHNOLOGY INC.
    Inventors: Young Jun Roh, Min Sik Shin, Sung Hoon Kang, Tae Seok Oh
  • Patent number: 11830897
    Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 28, 2023
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Yunfei Gao, Tae Seok Oh, Jinwen Xiao
  • Publication number: 20230240627
    Abstract: A computed tomography (CT) apparatus includes a gantry including a rotation device which has a ring shape and is rotatable about an axis of rotation, a plurality of light sources configured to emit X-rays to a subject, at least one detector provided on the rotation device and configured to detect X-rays passing through the subject, and one or more processors. The at least one processors are configured to rotate the rotation device in a first rotation direction by an angle of rotation determined based on a total number of the plurality of light sources, emit X-rays to the subject and detect X-rays passing through the subject during the rotation of the rotation device in the first rotation direction, and rotate the rotation device by the determined rotation angle in a second rotation direction.
    Type: Application
    Filed: June 26, 2020
    Publication date: August 3, 2023
    Applicant: KOH YOUNG TECHNOLOGY INC.
    Inventors: Young Jun ROH, Min Sik SHIN, Sung Hoon KANG, Tae Seok OH
  • Publication number: 20230215885
    Abstract: An imaging pixel design is provide with a photo-sensor block structure that facilitates dynamic control of well capacity in the photodiode region (i.e., a “well capacity adjustment (WCA) gate photo-sensor block”). The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Inventors: Yunfei GAO, Tae Seok OH
  • Publication number: 20230094943
    Abstract: A trench-gate source-follower (TGSF) transistor is described, such as for integration with image sensor pixels. The TGSF transistor is at least partially built into a trench etched into a substrate. A contiguous doped region is implanted around the inner walls of the trench to form a buried-trench current channel. A trench-gate is formed to have at least a buried portion that fills the volume of the trench. A gate oxide layer can be disposed between the buried portion of the trench-gate and the buried-trench current channel. Drain and source regions are formed on either end of the trench-gate. Activating the trench-gate causes current to flow between the drain and source regions via the buried-trench current channel around the buried portion of the trench-gate. The geometry of the buried-trench current channel can effectively increase the width of the active region of the source-follower transistor without increasing its physical layout width.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Yunfei GAO, Tae Seok OH, Jinwen XIAO
  • Patent number: 11610923
    Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 21, 2023
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Yunfei Gao, Tae Seok Oh, Jinwen Xiao
  • Publication number: 20230013187
    Abstract: Techniques are described for implementing a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture, such as for reducing noise in low-light application contexts. The split-SEL CIS pixel physical architecture can include a pixel block with one or more photodiodes. Above the photodiodes, there can be: a first oxide diffusion region with a reset block and a gain block disposed thereon; and a second oxide diffusion region with a select block disposed thereon. Below the photodiodes, there can be a third oxide diffusion region with a source follower (SF) block (e.g., a square-gate SF transistor) disposed thereon. A trace can be routed through the set of photodiodes to couple the source of the SF block with the select block. The architecture permits an appreciable increase in the physical gate length and/or other features.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Inventors: Yunfei GAO, Yu Hin Desmond CHEUNG, Tae Seok OH, Jinwen XIAO
  • Publication number: 20220265227
    Abstract: A computed tomography (CT) apparatus according to various embodiments may include a gantry including a first rotation device, a second rotation device and a third rotation device which have a ring shape, share an axis of rotation, and are rotatable independently of one another, a plurality of first light sources provided on the first rotation device at regular intervals and configured to emit X-rays to a subject, a plurality of second light sources provided on the second rotation device at regular intervals and configured to emit X-rays to the subject, a detector provided on a region of the third rotation device and configured to detect X-rays passing through the subject, and one or more processors.
    Type: Application
    Filed: June 26, 2020
    Publication date: August 25, 2022
    Applicant: KOH YOUNG TECHNOLOGY INC.
    Inventors: Young Jun ROH, Min Sik SHIN, Sung Hoon KANG, Tae Seok OH
  • Publication number: 20220257201
    Abstract: A computed tomography (CT) apparatus includes a gantry with a first rotation device and a second rotation device, a plurality of light sources configured to emit X-rays to a subject, a detector configured to detect X-rays passing through the subject, and one or more processors. The one or more processors may be configured to rotate the first rotation device in a first rotation direction by an angle of rotation determined based on a total number of the plurality of light sources, emit X-rays to the subject by using at least one of the plurality of light sources and detect X-rays passing through the subject during the rotation of the first rotation device in the first rotation direction, and rotate the first rotation device by the determined angle of rotation in a second rotation direction.
    Type: Application
    Filed: June 26, 2020
    Publication date: August 18, 2022
    Applicant: KOH YOUNG TECHNOLOGY INC.
    Inventors: Young Jun ROH, Min Sik SHIN, Sung Hoon KANG, Tae Seok OH
  • Publication number: 20220238580
    Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.
    Type: Application
    Filed: November 11, 2021
    Publication date: July 28, 2022
    Inventors: Yunfei GAO, Tae Seok OH, Jinwen XIAO
  • Publication number: 20220216252
    Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Yunfei GAO, Tae Seok OH, Jinwen XIAO
  • Publication number: 20220199663
    Abstract: A saddle-gate source follower transistor is described, such as for integration with in-pixel circuitry of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The saddle-gate source-follower transistor structure can include a channel region having a three-dimensional geometry defined on its axial sides by trenches. A gate oxide layer is formed over the top and axial sides of the channel region, and a saddle-gate structure is formed on the gate oxide layer. As such, the saddle-gate structure includes a seat portion extending over the top of the channel region, and first and second fender portions extending over the first and second axial sides of the channel region, such that the first and second fender portions are buried below an upper surface of the semiconductor substrate (e.g., buried into trenches formed in side isolation regions).
    Type: Application
    Filed: November 15, 2021
    Publication date: June 23, 2022
    Inventors: Yunfei GAO, Tae Seok OH, Jinwen XIAO
  • Patent number: 10943939
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 9, 2021
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 10523302
    Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 31, 2019
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Inkyu Lee, Jong-Ho Oh, Bong-Jin Kim, Tae-Yeong Kim, Min-Ki Ahn, Tae-Seok Oh, Seok-Ju Jang
  • Publication number: 20190189668
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventors: BYUNG-JUN PARK, CHANG-ROK MOON, SEUNG-HUN SHIN, SEONG-HO OH, TAE-SEOK OH, JUNE-TAEG LEE