Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-generation (4G) communication system such as long term evolution (LTE). Disclosed are an apparatus and a method for a permutation of a block code in a wireless communication system. A method of operating a transmitting node in a wireless communication system includes: determining a permutation matrix according to a block code scheme; generating symbols corresponding to a plurality of antennas based on the block code scheme and the permutation matrix; and transmitting the symbols to a receiving node through the plurality of antennas. The permutation matrix is determined based on a number of blocks and an arrangement structure of the plurality of antennas, and the number of blocks comprises a number of sub-blocks within a code block corresponding to the permutation matrix.

Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-generation (4G) communication system such as long term evolution (LTE). Disclosed are an apparatus and a method for a permutation of a block code in a wireless communication system. A method of operating a transmitting node in a wireless communication system includes: determining a permutation matrix according to a block code scheme; generating symbols corresponding to a plurality of antennas based on the block code scheme and the permutation matrix; and transmitting the symbols to a receiving node through the plurality of antennas. The permutation matrix is determined based on a number of blocks and an arrangement structure of the plurality of antennas, and the number of blocks comprises a number of sub-blocks within a code block corresponding to the permutation matrix.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

Abstract: An image sensor chip includes a first wafer and a second wafer. The first wafer includes an image sensor having a plurality of sub-pixels, each of which is configured to detect at least one photon and output a sub-pixel signal according to a result of the detection. The image processor is configured to process sub-pixel signals for each sub-pixel and generate image data. The first wafer and the second wafer are formed in a wafer stack structure.

Abstract: An image sensor includes a pixel array and a row driver block. The pixel array includes a plurality of subpixel groups, each including a plurality of subpixels. Each of the plurality of subpixels is configured to generate a subpixel signal corresponding to photocharge accumulated in response to a photon. The row driver block is configured to generate a first control signal to control the subpixels included in each of the plurality of subpixel groups to accumulate the photocharge in parallel from a first time point to a second time point.

Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

Abstract: A binary complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array and a readout circuit. The pixel array includes at least one pixel having a plurality of sub-pixels. The readout circuit is configured to quantize a pixel signal output from the pixel using a reference signal. The pixel signal corresponds to sub-pixel signals output from sub-pixels, from among the plurality of sub-pixels, activated in response to incident light.

Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.

Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.

Abstract: An image sensor includes a pixel array and a row driver block. The pixel array includes a plurality of subpixel groups, each including a plurality of subpixels. Each of the plurality of subpixels is configured to generate a subpixel signal corresponding to photocharge accumulated in response to a photon. The row driver block is configured to generate a first control signal to control the subpixels included in each of the plurality of subpixel groups to accumulate the photocharge in parallel from a first time point to a second time point.

Abstract: A binary complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array and a readout circuit. The pixel array includes at least one pixel having a plurality of sub-pixels. The readout circuit is configured to quantize a pixel signal output from the pixel using a reference signal. The pixel signal corresponds to sub-pixel signals output from sub-pixels, from among the plurality of sub-pixels, activated in response to incident light.

Abstract: An image sensor chip includes a first wafer and a second wafer. The first wafer includes an image sensor having a plurality of sub-pixels, each of which is configured to detect at least one photon and output a sub-pixel signal according to a result of the detection. The image processor is configured to process sub-pixel signals for each sub-pixel and generate image data. The first wafer and the second wafer are formed in a wafer stack structure.

Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

Abstract: An image sensor is provided. The image sensor includes a well of a second conductivity type formed on an impurity layer of a first conductivity type, source and drain regions of the first conductivity type, formed in the well to be spaced apart from each other, a first photo diode of the first conductivity type formed in the well to overlap the source and drain regions, a second photo diode of the first conductivity type formed so as not to overlap the source and drain regions and formed to be adjacent to the first photo diode, and a gate electrode formed on the first and second photo diodes.