Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.

Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Abstract: In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract: In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Abstract: A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ECC) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ECC corrector separated from the ECC calculator, the ECC corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits.

Abstract: A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Abstract: A semiconductor memory device capable of reducing the number of pads is provided. The semiconductor memory device may include a pad, a power supply voltage generating circuit and a voltage selection circuit. The power supply voltage generating circuit may generate one or more power supply voltages, which may be used in a semiconductor device. The voltage selection circuit may select one of the power supply voltages in response to test mode signals to provide the selected power supply voltage to the pad. The voltage selection circuit may include a voltage level regulating circuit to convert voltage levels of the test mode signals to generate gate control signals and metal-oxide semiconductor (MOS) transistors connected to the power supply voltages, respectively. The MOS transistors may be selectively turned on in response to the gate control signals to provide the selected power supply voltage to the pad.

Abstract: A semiconductor memory device capable of reducing the number of pads is provided. The semiconductor memory device may include a pad, a power supply voltage generating circuit and a voltage selection circuit. The power supply voltage generating circuit may generate one or more power supply voltages, which may be used in a semiconductor device. The voltage selection circuit may select one of the power supply voltages in response to test mode signals to provide the selected power supply voltage to the pad. The voltage selection circuit may include a voltage level regulating circuit to convert voltage levels of the test mode signals to generate gate control signals and metal-oxide semiconductor (MOS) transistors connected to the power supply voltages, respectively. The MOS transistors may be selectively turned on in response to the gate control signals to provide the selected power supply voltage to the pad.

Abstract: A semiconductor memory device having a bitline coupling scheme capable of preventing sensing speed from lowering due to variations in an external power supply is provided. The semiconductor memory device includes a memory cell array which includes a plurality of memory cells, a bitline and a complementary bitline which are connected to the memory cell array, a coupling capacitor one end of which is connected to either the bitline or the complementary bitline and the other end of which a control signal is applied to, a bitline sensing amplifier which senses and amplifies a difference in the voltage between the bitline and the complementary bitline, and a control circuit which generate the control signal. Here, an internal power supply generated by dropping an external power supply applied from the outside of the semiconductor memory device is used as a power supply of the control circuit.

Abstract: A semiconductor memory device having a bitline coupling scheme capable of preventing sensing speed from lowering due to variations in an external power supply is provided. The semiconductor memory device includes a memory cell array which includes a plurality of memory cells, a bitline and a complementary bitline which are connected to the memory cell array, a coupling capacitor one end of which is connected to either the bitline or the complementary bitline and the other end of which a control signal is applied to, a bitline sensing amplifier which senses and amplifies a difference in the voltage between the bitline and the complementary bitline, and a control circuit which generate the control signal. Here, an internal power supply generated by dropping an external power supply applied from the outside of the semiconductor memory device is used as a power supply of the control circuit.

Abstract: A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

Abstract: Disclosed herewith is a prosthetic foot. The prosthetic foot is to be connected to a pylon that is utilized for the substitution of the shinbone of an amputee. The prosthetic foot includes an ankle portion to be secured to the pylon. A plurality of curved portions are extended from one end of the ankle portion. A sole portion is extended from one end of the curved portions. The ankle portion, the curved portions and the sole portion form a single integrated plate spring structure.

Abstract: A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

Abstract: A semiconductor memory device having a fixed CAS latency during a normal operation and various CAS latencies during a test mode. The semiconductor memory device a master signal generator for generating a master signal in response to a power-up signal and a latency test signal. A plurality of fuse information units generate fuse information signals in response to the power-up signal and the master signal. A plurality of mode register set (MRS) address information units receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal. A CAS latency determining unit generates CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide a fixed CAS latency during a normal mode of operation of the semiconductor device and varying CAS latencies during a test mode of operation of the semiconductor device.

Abstract: A semiconductor memory device having a fixed CAS latency during a normal operation and various CAS latencies during a test mode. The semiconductor memory device a master signal generator for generating a master signal in response to a power-up signal and a latency test signal. A plurality of fuse information units generate fuse information signals in response to the power-up signal and the master signal. A plurality of mode register set (MRS) address information units receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal. A CAS latency determining unit generates CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide a fixed CAS latency during a normal mode of operation of the semiconductor device and varying CAS latencies during a test mode of operation of the semiconductor device.

Abstract: A semiconductor device having an input circuit well-suited for use in a stacked-chip configuration, results in a reduction in input capacitance, and an overall improvement in transmission speed. The semiconductor device includes at least two bonding pads which receive external electrical input signals from a shared common external pin, and at least two internal circuits, each electrically coupled to a corresponding bonding pad by a signal transmission line. The semiconductor device further includes at least two protective elements, each electrically coupled to a corresponding signal transmission line, each for protecting the internal circuits from excessive electrical transmission characteristics in the input signal. At least two fuses are electrically coupled in series between the corresponding protective element and signal transmission line. The fuses are each capable of being opened to electrically insulate the protective elements from the bonding pads and the internal circuits.