Abstract: A method of transmitting data from a VPN (Virtual Private Network) server to an MN (Mobile Node). The MN requests a VPN service registration to an FA (Foreign Agent) to which the MN belongs. The FA notifies ISP (Internet Service Provider) routers connected to the FA that the MN has requested the VPN service registration. Upon receipt of VPN service data destined for the MN from the VPN server, the FA routes the VPN service data to the MN.

Abstract: A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

Abstract: Memory modules, and related memory module sockets, can include a plurality of connector pins adjacent to a first edge of the memory module that are configured to conduct a plurality of first signals to or from the memory module via the first edge and a plurality of first conductors adjacent to a second edge of the memory module that are configured to conduct a plurality of second signals to or from the memory module via the second edge.

Abstract: A method of transmitting data from a Virtual Private Network (“VPN”) server to a Mobile Node (“MN”) is provided. Upon sensing generation of data destined for the MN in the VPN server, a Customer Premise Equipment (“CPE”) router requests an Internet Service Provider (“ISP”) router connected to a VPN to search for an address of a Foreign Agent (“FA”) to which the MN belongs. The ISP router searches for the FA address through a Home Agent (“HA”) and routes the data to the FA identified by the searched FA address. The FA then locates the MN and forwards the data to the MN.

Abstract: A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

Abstract: A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

Abstract: Disclosed is a regional tunnel management method in a mobile communication system using Mobile IP. A mobile node transmits a location registration request to a first GGSN (Gateway GPRS (General Packet Radio Service) Support Node), upon receiving information indicating that the first GGSN supports a foreign agent function and also receiving an Agent Advertisement message with an address of a second GGSN. The information and the Agent Advertisement message are transmitted by the first GGSN. The first GGSN transmits the location registration request to the second GGSN. The second GGSN registers an address of the first GGSN to which the mobile node belongs, and then transmits to a home agent the Location Information message indicating an address of the first GGSN to which the mobile node belongs.

Abstract: A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

Abstract: Disclosed is a system providing a VPN service by connecting a VPN (virtual Private Network) to a mobile communication network. A home agent (HA) stores location information of a mobile node (MN) and information on whether the MN is registered in the VPN. A foreign agent (FA) transmits a location registration request message to the HA by receiving location registration information of the MN, and transmits data to an ISP (Internet Service Provider) router in the same subnet upon receiving a VPN service request. A server provides the VPN service and a router network connects the VPN to the FA. The router network includes a server for searching an edge IP router in the network using an address of the FA. The HA prevents an MN from accepting a call request received from a specific node in an IP network while the MN is performing a VPN service.

Abstract: A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit board. The bus lines are connected to the module tabs, respectively, and are connected to the memory chips. Each of the bus lines is formed a closed circuit loop. Each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop. Since each bus line on the memory module forms a closed loop, skew does not occur between control signals or output data, which are transmitted through the bus line.

Abstract: There is provided a handover method for a mobile node (MN) having a mobile IP (Internet Protocol) address in a mobile communication system. When a handover occurs as the MN moves from the area of a first FA to the area of a second FA adjacent to the first FA, the second FA transmits a Binding Update message including the IP address of the second FA and an acknowledgement request to the first FA. In response to the Binding Update message, the first FA transmits a Binding Acknowledge message to the second FA, including a field indicative of the IP tunneling capability of a router connected to a corresponding node (CN) to which the MN connects a call.

Abstract: An integrated circuit memory system includes one or more memory modules in which at least one of the memory modules is responsive to a control signal and has delay control information stored thereon. The memory system further includes a memory controller that is configured to generate the control signal in response to the delay control information.

Abstract: A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit board. The bus lines are connected to the module tabs, respectively, and are connected to the memory chips. Each of the bus lines is formed a closed circuit loop. Each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop. Since each bus line on the memory module forms a closed loop, skew does not occur between control signals or output data, which are transmitted through the bus line.

Abstract: Memory modules are discloses which can include a plurality of connector pins adjacent to a first edge of the memory module that are configured to conduct a plurality of first signals to or from the memory module via the first edge and a plurality of first conductors adjacent to a second edge of the memory module that are configured to conduct a plurality of second signals to or from the memory module via the second edge. Related memory module sockets are also disclosed.

Abstract: A method for transmitting a data packet from a mobile node to a correspondent node through a foreign agent while maintaining security is disclosed. A correspondent node transmits a first data packet for communication with a mobile node to the home agent. Upon receipt of the first data packet from the home agent, the foreign agent transmits the first data packet to the mobile node through a radio channel. The home agent transmits the IP address of the foreign agent to the correspondent node after transmitting the first data packet to the foreign agent. The correspondent node transmits tunneling indication information indicating whether it can decapsulate a data packet encapsulated by the foreign agent to the foreign agent after receiving the IP address of the foreign agent from the home agent.

Abstract: Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the memory interface system uses a terminal voltage that is independent of the supply voltages of the memory and the memory controller, the interface system may be unaffected by voltage differences between the memory supply voltage and the memory controller supply voltage.

Abstract: Reference voltage generators can be made relatively insensitive to variations in threshold voltages due to device fabrication processes by providing first and second transistors of the same conductivity type that are connected to one another and between first and second power supply voltages, such that the first transistor operates below the threshold voltage thereof and the second transistor operates above the threshold voltage thereof. The first transistor includes a gate that is coupled to a first node connected to a first power supply voltage and that is connected between an output reference voltage terminal and a second node that is connected to a second power supply voltage. The second transistor includes a gate that is coupled to the second node and is connected between the first node and the second power supply voltage.

Abstract: A flash memory includes an array of memory cells having sources, drains, floating gates, and control gates. The array includes a conductive plate formed over the memory cells to affect a capacitive coupling between the memory cells and the conductive plate. A first voltage source provides a first voltage to the control gate of a selected one of the memory cells. A second voltage source provides a second voltage to the conductive plate after the control gate of the selected one of the memory cells has been charged up to a predetermined voltage level. Additionally, the flash memory includes a switching circuit to transfer the first and second voltages to the control gate of the selected memory cell and the conductive plate, respectively, responsive to a first and second control signals.

Abstract: Reference voltage generators can be made relatively insensitive to variations in threshold voltages due to device fabrication processes by providing first and second transistors of the same conductivity type that are connected to one another and between first and second power supply voltages, such that the first transistor operates below the threshold voltage thereof and the second transistor operates above the threshold voltage thereof. The first transistor includes a gate that is coupled to a first node connected to a first power supply voltage and that is connected between an output reference voltage terminal and a second node that is connected to a second power supply voltage. The second transistor includes a gate that is coupled to the second node and is connected between the first node and the second power supply voltage.

Abstract: A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.