Patents by Inventor Tae-Wan Lim
Tae-Wan Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133959Abstract: A method for adjusting a current of a battery includes obtaining one or more parameters of a battery including the current of the battery, a voltage and a temperature of the battery, determining a first correction parameter relating to a variation in current due to charging and discharging of the battery, based on at least a portion of the one or more parameters, determining a difference between an electrolyte concentration of an anode surface and an electrolyte concentration of a cathode surface of the battery, based on at least a portion of the one or more parameters, determining a temperature parameter based on the temperature of the battery, determining a second correction parameter relating to a temperature of the battery, based on the difference and the temperature parameter, and determining a correction value for the current of the battery based on the first correction parameter and the second correction parameter.Type: ApplicationFiled: April 9, 2023Publication date: April 25, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju Wan LIM, Jinho KIM, Tae Won SONG
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Patent number: 11925015Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.Type: GrantFiled: September 18, 2020Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yong Park, Kee-Jeong Rho, Hyeong Park, Tae-Wan Lim
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Publication number: 20210005615Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Inventors: SANG-YONG PARK, KEE-JEONG RHO, HYEONG PARK, TAE-WAN LIM
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Patent number: 10811421Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.Type: GrantFiled: September 22, 2017Date of Patent: October 20, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
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Patent number: 10700088Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.Type: GrantFiled: December 14, 2018Date of Patent: June 30, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jongwon Kim, Keejeong Rho, Jin-Yeon Won, Tae-Wan Lim, Woohyun Park
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Patent number: 10608091Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.Type: GrantFiled: September 4, 2018Date of Patent: March 31, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Wan Lim, Hojong Kang, Joowon Park
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Publication number: 20190139984Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.Type: ApplicationFiled: December 14, 2018Publication date: May 9, 2019Inventors: Jongwon KIM, Keejeong Rho, Jin-Yeon Won, Tae-Wan Lim, Woohyun Park
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Publication number: 20190019872Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.Type: ApplicationFiled: September 4, 2018Publication date: January 17, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Tae-Wan LIM, Hojong Kang, Joowon Park
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Patent number: 10181476Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.Type: GrantFiled: March 31, 2016Date of Patent: January 15, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jongwon Kim, Keejeong Rho, Jin-Yeon Won, Tae-Wan Lim, Woohyun Park
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Patent number: 10103236Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.Type: GrantFiled: May 10, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Wan Lim, Hojong Kang, Joowon Park
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Publication number: 20180026041Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.Type: ApplicationFiled: September 22, 2017Publication date: January 25, 2018Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
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Patent number: 9780096Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.Type: GrantFiled: December 10, 2015Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
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Publication number: 20170271463Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.Type: ApplicationFiled: May 10, 2017Publication date: September 21, 2017Inventors: Tae-Wan LIM, Hojong KANG, Joowon PARK
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Patent number: 9711603Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.Type: GrantFiled: December 2, 2015Date of Patent: July 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Wan Lim, Hojong Kang, Joowon Park
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Patent number: 9600357Abstract: Disclosed is an error detection method of fail safe software, the method including outputting a pulse signal according to an operation state of fail safe software monitoring a fail safe function of a motor control device; determining presence or absence of an error of the fail safe software using a frequency of the pulse signal; and controlling an output of the motor control device based on the presence or absence of the error of the fail safe software. Accordingly, even though whether the motor control device is in an abnormal state is not determined due to an error of the fail safe software, it is possible to prevent excessive motor torque from occurring.Type: GrantFiled: February 10, 2015Date of Patent: March 21, 2017Assignee: HYUNDAI MOBIS CO., LTD.Inventor: Tae Wan Lim
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Publication number: 20160293627Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.Type: ApplicationFiled: March 31, 2016Publication date: October 6, 2016Inventors: Jongwon Kim, Keejeong Rho, Jin-Yeon Won, Tae-Wan Lim, Woohyun Park
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Publication number: 20160204111Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.Type: ApplicationFiled: December 10, 2015Publication date: July 14, 2016Inventors: Sang-Yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
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Publication number: 20160172296Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.Type: ApplicationFiled: December 2, 2015Publication date: June 16, 2016Inventors: Tae-Wan LIM, Hojong Kang, Joowon Park
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Publication number: 20160147584Abstract: Disclosed is an error detection method of fail safe software, the method including outputting a pulse signal according to an operation state of fail safe software monitoring a fail safe function of a motor control device; determining presence or absence of an error of the fail safe software using a frequency of the pulse signal; and controlling an output of the motor control device based on the presence or absence of the error of the fail safe software. Accordingly, even though whether the motor control device is in an abnormal state is not determined due to an error of the fail safe software, it is possible to prevent excessive motor torque from occurring.Type: ApplicationFiled: February 10, 2015Publication date: May 26, 2016Inventor: Tae Wan LIM
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Patent number: 9330966Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.Type: GrantFiled: December 7, 2011Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Young Kim, Jun-Eui Song, Tae-Wan Lim