Abstract: Provided are a photodetector (PD) using a graphene thin film and nanoparticles and a method of fabricating the same. The PD includes a graphene thin film having a sheet shape formed by means of a graphene deposition process using a vapor-phase carbon (C) source and a nanoparticle layer formed on the graphene thin film and patterned to define an electrode region of the graphene thin film, the nanoparticle layer being formed of nanoparticles without a matrix material. The PD has a planar structure using the graphene thin film as a channel and an electrode and using nanoparticles as a photovoltaic material (capable of forming electron-hole pairs due to photoelectron-motive force caused by ultraviolet (UV) light). Since the PD has a very simple structure, the PD may be fabricated at low cost with high productivity. Also, the PD includes the graphene thin film to reduce power consumption.

Abstract: A solar cell using a p-i-n nanowire that may generate light by absorbing solar light in a wide wavelength region efficiently without generating light loss and may be manufactured with a simplified process and low cost.

Abstract: An electrophoretic display includes a substrate on which image gate lines and image signal lines are formed to intersect one another. An image switching thin-film transistor (TFT) is formed on the substrate and electrically connected to the image gate lines and the image signal lines. A sensing TFT is formed on the substrate and configured to sense infrared (IR) light and generate an IR sensing signal. An output switching TFT is formed on the substrate and connected to the sensing TFT. The output switching TFT outputs position information from the IR sensing signal. An IR filter insulating layer is formed on the substrate to cover the sensing TFT and configured to transmit only the IR light. A pixel electrode is formed on the IR filter insulating layer and electrically connected to the image switching TFT. An electrophoretic film is formed on the pixel electrode and includes a plurality of micro-capsules having pigment particles with positive and negative electrical charges.

Abstract: Provided are an electronic device and methods of fabricating the same, the electronic device include a device-substrate, a stacked structure, and an electrode. The stacked structure includes a graphene thin film between a first insulator and a second insulator. The electrode is disposed over the stacked structure.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: According to an embodiment of the present invention, an OLED display includes a substrate, a first electrode, a hole transport layer, a hole blocking layer, an emitting layer, and a second electrode. The first electrode is formed on the substrate. The hole transport layer is formed on the first electrode and includes a first material having a first highest occupied molecular orbital (HOMO) level and a first lowest unoccupied molecular orbital (LUMO) level. The hole blocking layer is formed on the hole transport layer and includes a second material having a second HOMO level and a second LUMO level. The emitting layer is formed on the hole blocking layer and includes a third material having a third HOMO level and a third LUMO level. The second electrode is formed on the emitting layer. Herein, the second HOMO level is higher than the first HOMO level and the third HOMO level.

Abstract: Example embodiments are directed to an electronic device and a method for manufacturing the same. The electronic device includes a polymer thin film and an electrode. The polymer thin film includes nanoparticles. The electrode is formed by attaching a graphene thin film of a sheet shape formed through graphene deposition using a vapor carbon supply source to the polymer thin film. In the method, a graphene thin film of a sheet shape is formed through graphene deposition using a vapor carbon supply source. A polymer solution with distributed nanoparticles is prepared. The polymer solution with distributed nanoparticles is spin-coated on a substrate. A polymer thin film comprising the nanoparticles is formed by drying the spin-coated polymer solution. An electrode is formed by attaching the graphene thin film onto the polymer thin film.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A nonvolatile organic bistable memory device includes a substrate, a lower electrode disposed on the substrate, a lower charge injection layer disposed on the lower electrode, an insulating polymer layer including nanoparticles disposed on the lower charge injection layer, an upper charge injection layer disposed on the insulating polymer layer, and an upper electrode disposed on the upper charge injection layer. The lower and upper charge injection layers each include fullerenes and/or carbon nanotubes.

Abstract: Provided may be a method of fabricating a flash memory device having metal nano particles. The method of manufacturing a flash memory device may include forming a metal oxide thin layer on a semiconductor substrate, forming a floating gate of an amorphous metal silicon oxide thin layer by performing a thermal treatment process on the semiconductor substrate where the metal oxide thin layer is formed, and forming metal nano particles in the floating gate by projecting an electron beam on the floating gate, the metal nano particles being surrounded by a silicon oxide layer.

Abstract: Provided may be a method of fabricating a flash memory device having metal nano particles. The method of manufacturing a flash memory device may include forming a metal oxide thin layer on a semiconductor substrate, forming a floating gate of an amorphous metal silicon oxide thin layer by performing a thermal treatment process on the semiconductor substrate where the metal oxide thin layer is formed, and forming metal nano particles in the floating gate by projecting an electron beam on the floating gate, the metal nano particles being surrounded by a silicon oxide layer.

Abstract: A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

Abstract: An organic light emitting device according to embodiment of the present invention comprises: a substrate; a first electrode formed on the substrate; a light-emitting member formed on the first electrode, and comprising multi-layer structure; and a second electrode formed on the light-emitting member, wherein the second electrode comprises Mg—Ag alloy which contains Mg of 1-10 wt % and a concentration gradient of the Mg—Ag alloy is formed from the top of the emitting-light member.

Abstract: A manufacturing method of an organic light emitting diode (“OLED”) includes forming an anode on a substrate, forming an inorganic buffer layer on the anode, forming a hole transport layer on the buffer layer, forming a light emission layer on the hole transport layer, forming an electron transport layer on the light emission layer, and forming a cathode on the electron transport layer. The forming an inorganic buffer layer includes thermal evaporation and oxidation.

Abstract: In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer thin film located on the tunneling dielectric layer, metal or metal oxide nano-crystals embedded in the organic polymer thin film, and a gate located on the organic polymer thin film.

Abstract: A flash memory device with a nanoscale floating gate and a method of manufacturing thereof are disclosed. At least one embodiment of the present invention provides a much simpler and easier method of manufacturing nanocrystals (or nanocrystallines) for the flash memory device than the conventional method. Since the nanocrystals are homogeneously dispersed as a polymer layer without agglomeration, size and density of the nanoparticles may be controlled. Additionally, one embodiment of the present invention provides memory devices with nanoscale floating gates, and related methods of manufacture, of high efficiency and cost effectiveness by employing electrically and chemically more stable nanoscale floating gates compared to conventional ones.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A nonvolatile organic bistable memory device includes a substrate, a lower electrode disposed on the substrate, a lower charge injection layer disposed on the lower electrode, an insulating polymer layer including nanoparticles disposed on the lower charge injection layer, an upper charge injection layer disposed on the insulating polymer layer, and an upper electrode disposed on the upper charge injection layer. The lower and upper charge injection layers each include fullerenes and/or carbon nanotubes.

Abstract: Provided may be a gate pattern, flash memory and methods of manufacturing and operating the same. A gate pattern may include a floating gate on a tunneling dielectric layer, an inter-gate dielectric layer on the floating gate, a first control gate on the inter-gate dielectric layer, and a second control gate on the inter-gate dielectric layer and spaced apart from the first control gate. Each of the control gates sets four states according to an application time of a program voltage applied to the control gates. Thus, one control gate may program 2-bit data.