Patents by Inventor Tae-Yeong Kim

Tae-Yeong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200075360
    Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.
    Type: Application
    Filed: July 10, 2019
    Publication date: March 5, 2020
    Inventors: Jun-hyung KIM, Sung-hyup KIM, Tae-yeong KIM
  • Publication number: 20200055296
    Abstract: A wafer bonding apparatus including: a lower chuck to which a lower wafer is secured at a peripheral portion of the lower chuck; an upper chuck to which an upper wafer is secured; a bonding initiator for pressuring a central portion of the upper wafer until the central portion of the upper wafer reaches a central portion of the lower wafer, thereby initiating a bonding process of the upper and the lower wafers by deforming the upper wafer; and a bonding controller for controlling a bonding speed between a peripheral portion of the upper wafer and a peripheral portion of the lower wafer such that the upper wafer becomes un-deformed prior to bonding the peripheral portion of the upper wafer and the peripheral portion of the lower wafer.
    Type: Application
    Filed: April 17, 2019
    Publication date: February 20, 2020
    Inventors: Tae-Yeong KIM, Jun-Hyung KIM, Hoe-Chul KIM, Hoon-Joo NA, Kwang-Jin MOON
  • Publication number: 20200013643
    Abstract: A wafer bonding apparatus includes a first bonding chuck to fix a first wafer on a first surface thereof, a second bonding chuck to fix a second wafer on a second surface thereof facing the first surface, a bonding initiation member at a center of the first bonding chuck to push the first wafer towards the second surface, and a membrane member including a protrusion protruding from a center portion of the second surface towards the first surface, and a planar portion defining the protrusion on an outer region surrounding the center portion.
    Type: Application
    Filed: February 15, 2019
    Publication date: January 9, 2020
    Inventors: Jun-hyung KIM, Sung-hyup KIM, Tae-yeong KIM
  • Patent number: 10523302
    Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 31, 2019
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Inkyu Lee, Jong-Ho Oh, Bong-Jin Kim, Tae-Yeong Kim, Min-Ki Ahn, Tae-Seok Oh, Seok-Ju Jang
  • Patent number: 10468400
    Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil Kyu Kang, Seok Ho Kim, Tae Yeong Kim, Kwang Jin Moon, Ho Jin Lee
  • Publication number: 20190189593
    Abstract: A substrate bonding apparatus and a method of bonding substrates, the apparatus including an upper chuck securing a first substrate onto a lower surface thereof such that the first substrate is downwardly deformed into a concave surface profile; a lower chuck arranged under the upper chuck and securing a second substrate onto an upper surface thereof such that the second substrate is upwardly deformed into a convex surface profile; and a chuck controller controlling the upper chuck and the lower chuck to secure the first substrate and the second substrate, respectively, and generating a shape parameter for changing a shape of the second substrate to the convex surface profile from a flat surface profile.
    Type: Application
    Filed: September 19, 2018
    Publication date: June 20, 2019
    Inventors: Jun-Hyung KIM, Sung-Hyup KIM, Kyeong-Bin LIM, Seok-Ho KIM, Tae-Yeong KIM
  • Patent number: 10200889
    Abstract: Disclosed in the present application is a method for a terminal receiving data in a wireless communication system. Specifically, the method comprises the steps of determining at least one transmission subject for the data among one or more auxiliary nodes and a base station; receiving a distributed code from the determined at least one transmission subject; and obtaining the data from the distributed code, wherein the at least one transmission subject is determined based on the sum of the distributed codes stored in the auxiliary nodes and the number of auxiliary nodes existing within a predetermined distance from the terminal.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 5, 2019
    Assignees: LG ELECTRONICS INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Hanbyul Seo, Wan Choi, Dongin Kim, Bi Hong, Hojin Song, Tae Yeong Kim
  • Publication number: 20180370210
    Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.
    Type: Application
    Filed: December 18, 2017
    Publication date: December 27, 2018
    Inventors: Tae-yeong Kim, Pil-kyu Kang, Seok-ho Kim, Kwang-jin Moon, Na-ein Lee, Ho-jin Lee
  • Publication number: 20180262255
    Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.
    Type: Application
    Filed: September 23, 2016
    Publication date: September 13, 2018
    Inventors: Inkyu LEE, Jong-Ho OH, Bong-Jin KIM, Tae-Yeong KIM, Min-Ki AHN, Tae-Seok OH, Seok-Ju JANG
  • Publication number: 20180226390
    Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 9, 2018
    Inventors: Pil Kyu KANG, Seok Ho KIM, Tae Yeong KIM, Kwang Jin MOON, Ho Jin LEE
  • Patent number: 9941243
    Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-yeong Kim, Pil-kyu Kang, Seok-ho Kim, Kwang-jin Moon, Ho-jin Lee
  • Patent number: 9935037
    Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil-kyu Kang, Ho-jin Lee, Byung-lyul Park, Tae-yeong Kim, Seok-ho Kim
  • Publication number: 20180054747
    Abstract: Disclosed in the present application is a method for a terminal receiving data in a wireless communication system. Specifically, the method comprises the steps of determining at least one transmission subject for the data among one or more auxiliary nodes and a base station; receiving a distributed code from the determined at least one transmission subject; and obtaining the data from the distributed code, wherein the at least one transmission subject is determined based on the sum of the distributed codes stored in the auxiliary nodes and the number of auxiliary nodes existing within a predetermined distance from the terminal.
    Type: Application
    Filed: March 18, 2016
    Publication date: February 22, 2018
    Applicants: LG ELECTRONICS INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Hanbyul SEO, Wan CHOI, Dongin KIM, Bi HONG, Hojin SONG, Tae Yeong KIM
  • Patent number: 9865581
    Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Hee Jang, Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Jum-Yong Park, Jin-Ho An, Kyu-Ha Lee, Yi-Koan Hong
  • Publication number: 20170358553
    Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.
    Type: Application
    Filed: January 24, 2017
    Publication date: December 14, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: TAE-YEONG KIM, Pil-kyu KANG, Seok-ho KIM, Kwang-jin MOON, Ho-jin LEE
  • Patent number: 9773660
    Abstract: Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-yeong Kim, Pil-kyu Kang, Byung-lyul Park, Jin-ho Park
  • Publication number: 20170207158
    Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 20, 2017
    Inventors: Pil-kyu KANG, Ho-jin LEE, Byung-lyul PARK, Tae-yeong KIM, Seok-ho KIM
  • Patent number: 9520361
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Joo-Hee Jang, Jin-Ho Chun
  • Publication number: 20160141249
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 19, 2016
    Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Joo-Hee Jang, Jin-Ho Chun
  • Publication number: 20160141282
    Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 19, 2016
    Inventors: Joo-Hee Jang, Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Jum-Yong Park, Jin-Ho An, Kyu-Ha Lee, Yi-Koan Hong