Abstract: A method of and apparatus for merging bit streams for seamless reproduction, and a recording medium for recording control information for bit stream merging. System clock reference (SCR) control information representing whether the SCR value of a bit stream is temporally discontinuous with respect to that of the preceding bit stream at the boundary between the two bit streams is recorded when the two bit streams are being merged. Thus, even where the SCR value at the boundary between merged bit streams rapidly changes when the merged bit stream is reproduced, seamless reproduction is accomplished. The SCR control information includes at least one among a control information identifier, a control information length indicator, a discontinuity indicator, and other information.

Abstract: A redundancy circuitry is used in a memory device for repairing defects in a packaged memory having registers by using antifuse.

Abstract: An MPEG2 moving picture and encoding/decoding system to provide digital copy protection of digital moving picture data. The MPEG2 moving picture encoder discrete cosine transforms a video input signal and uses a digital watermark inserter to embed digital watermark information on a frequency domain of the discrete cosine transformed video input signal. The MPEG2 moving picture decoder receives the encoded video output signal from the MPEG2 moving picture encoder and removes the embedded visual watermark information to locally decode the encoded video signal.

Abstract: An MPEG2 moving picture and encoding/decoding system to provide digital copy protection of digital moving picture data. The MPEG2 moving picture encoder discrete cosine transforms a video input signal and uses a digital watermark inserter to embed digital watermark information on a frequency domain of the discrete cosine transformed video input signal. The MPEG2 moving picture decoder receives the encoded video output signal from the MPEG2 moving picture encoder and removes the embedded visual watermark information to locally decode the encoded video signal.

Abstract: A repair circuit of a semiconductor memory device utilizes a plurality of current blocking circuits, each provided with a programmable anti-fuse, to reduce current consumption in DRAM devices, particularly during a normal operation mode.

Abstract: A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer surrounding the ledge; a base layer formed on the ledge of the collector layer; an ohmic cap layer on the emitter layer; an emitter layer formed in the center of the base layer; an emitter electrode formed on the ohmic cap layer; a base electrode formed on the base layer surrounding the emitter electrode; an insulating layer formed to cover the base electrode and to overlay on the insulating layer; a metal wire formed to cover the emitter electrode; and an air bridge brought in contact with the metal wire and electrically connected to an external pad lying on an ion-implanted isolation region.

Abstract: An apparatus for synchronously reproducing compressed and multiplexed data for multi-angle reproduction. The apparatus for synchronously reproducing multi-angle data includes a plurality of reproducers to receive a data stream in which multi-angle data is multiplexed for multi-angle reproduction, to separate, decode and reproduce data corresponding to a predetermined angle from the received data stream and to generate a reproduction ready notice signal indicating that data is ready for reproduction. One of the plurality of reproducers synchronizes data reproduction of the plurality of reproducers based on the reproduction ready notice signals generated by the other reproducers. Thus, images involving various angles at an instant can be provided to a user.

Abstract: A circuit conveniently sets the width of input/output data in a semiconductor memory device. The circuit includes a test mode signal generator for generating a test mode signal which sets a WCBR mode to a special test mode; a program signal generator for generating a program signal according to the test mode signal output from the test mode signal generator and a signal transmitted through a predetermined address line; a pair of anti-fuse programmers, each having an anti-fuse for outputting a programmed output value indicative of a program status of an anti-fuse programmed according to the program signal; and a decoder for decoding the signal output from the anti-fuse programmers to change the input/output data width of the semiconductor memory device. The anti-fuses are used for resetting the input/output data width at the package level of a manufactured memory device.

Abstract: There is disclosed an AC PDP comprising two plates. These two plates are opposite to each other with a plurality of parallel electrodes on one plate being across a plurality of parallel electrodes on the other. The space therebetween, sealed by a side wall, is filled with a discharge gas. A fluorescent layer is formed on the side of one of the plates in the sealed space. Opposite to the fluorescent layer, a dielectric multilayer structure is laminated on the electrodes and covered with an overcoat layer, wherein its sub-layers are of lower fluidity as they are nearer to the overcoat layer. This is accomplished by arranging the sub-layers in such a way that they may be higher in softening temperature as they are nearer to the overcoat layer. Since the sub-layers are made of glass materials, this softening temperature gradient is determined by the content of PbO and/or B.sub.2 O.sub.3 in each of the sub-layers, ranging from approximately 20-50% by weight and approximately 0.5-12.

Abstract: A variable bit rate MPEG2 video decoder having a variable rate fast playback function includes a variable rate fast playback processor with a portion determining the fullness of a video buffer according to the amount of data input to and output from the video buffer; a fast playback rate controller for calculating a variable rate control parameter S representing the number of bi-directional predicted (B) pictures to be restored within one group of pictures (GOP) for the fast playback mode and a parameter D representing the sequence of B pictures to be restored during the fast playback mode according to the total number (T) of pictures and the number (N) of B pictures within one GOP and the buffer's fullness output from the portion for determining the fullness of the video buffer; and an effective data detector and transmitter for detecting a picture start code to detect data of a picture layer, classifying data of pictures and counting the number of B pictures to transmit effective data for the fast playback

Abstract: An integrated circuit memory device includes first and second input buffers, and first and second input bus lines corresponding to the first and second input buffers. The first input buffer is connected to the first input bus line while a transfer gate is provided between the second input buffer and the second input bus line. The transfer gate connects the second input buffer with the second input bus line during a data input-output operation and disconnects the second input buffer from the second input bus line during a memory test operation. A coupling circuit couples the first and second input bus lines during the memory test operation so that a data value from the first input bus line is inverted and applied to the second input bus line responsive to a first value of an address buffer output during the memory test operation.

Abstract: A body structure of a microwave oven having a cooking chamber for cooking foods includes an electronic part mounting member for mounting electronic parts thereon, a partition wall formed with the electronic part mounting member in one body therewith, and a bottom plate arranged at one side of the partition wall, thereby covering the cooking chamber at a bottom position thereof.

Abstract: In a method for quantizing a moving picture signal and a circuit therefor, the method includes the steps of calculating horizontal and vertical gradients of first pixel values in a macroblock, determining each maximum value of the horizontal and vertical gradients, classifying the moving picture signal into complexity class if the maximum value is greater than a first threshold value and into edge class if the maximum value is greater than a second threshold value and is less than a third threshold value, calculating an activity value with respect to the first pixel values in the macroblock by calculating the sum of absolute values of DCT coefficients for four blocks in the macroblock, calculating an activity normalization coefficient, using the activity value of the macroblock and an average activity value of all pixels of the same picture type; and calculating a reference quantization step size produced by a backward rate control through a forward estimation considering coding efficiency and a visual charac

Abstract: A motion image coder is provided with a pre-filter for performing a pre-filtering which adaptively restricts the band for characteristics of the coded blocks. The pre-filtered result is used in determining quantization step size, thereby halving the quantization error causing a picture quality deterioration into a resolution error. Therefore, picture quality can be improved.

Abstract: In an encoder having a data formatter, a DCT circuit, a transmission rate controlling apparatus, a quantizer, a variable-length coder and an encoder buffer, for compressing a moving picture signal, the transmission rate controlling apparatus includes a segment complexity estimator for receiving outputs of the quantizer and variable-length coder and estimating the complexity of a segment of a current frame relative to a previous frame, a rate control adjustment coefficient calculator for receiving the output of the segment complexity estimator and calculating a rate control adjustment coefficient, a reference quantization coefficient calculator for receiving the rate control adjustment coefficient and the output of the encoder buffer and calculating a reference quantization coefficient, and an activity calculator for receiving the output of the data formatter, calculating activity by a macroblock unit, performing an operation on the calculated activity using the output of the reference quantization coefficient

Abstract: This invention relates to a method for automatic control of a microwave oven which can make precise cooking control available by classifying the cooking control into cases when cooking is completed below the boiling point of water, such as thawing or warming up, and cases when cooking is completed above the boiling point of water. For types of cooking which are complete without water boiling, the invention sets the initial cooking time period by determining the time it takes for the output voltage of a temperature detection sensor to reach a rise starting point. For types of cooking which include water boiling, the invention sets the initial cooking time period by determining the time it takes for the output voltage of the temperature detection sensor to reach a maximum rise point. The invention then sets an additional time period equivalent to the initial time period multiplied by a cooking constant corresponding to the type of cooking that is desired.

Abstract: A preprocessing device of a system that can record and reproduce the luminance and chrominance signal separated from a composite digital VTR signal is disclosed.The luminance/chrominance signal preprocessing device includes an analog/digital converter which samples a NTSC signal inputted as a composite video signal at a certain frequency, and converts the signal sample to a digital signal, a horizontal synchronizing separator that separates the horizontal synchronizing signal from the above NTSC signal, a PLL division that sends a clock signal fixed to the horizontal synchronizing signal outputted from the above horizontal synchronizing separator to the above analog/digital converter, and a luminance and chrominance signal outgoing from the above analog/digital converter is then separated into a luminance signal and a chrominance signal.