Patents by Inventor Taejoon Han

Taejoon Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10503850
    Abstract: Described herein are technologies to facilitate the generation and presentation of a map of an attribute of a substrate, such as a semiconductor wafer. Using the data of measured attribute (e.g., thickness, temperature, etc.) of a substrate, one or more of the described implementations generate data of non-measured (i.e., calculated) attributes to complete a map of the substrate using model parameters and a correlations model, such as a squared exponential Gaussian process model.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: December 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Morvay, Taejoon Han
  • Patent number: 10215704
    Abstract: Described herein are technologies to facilitate computed tomographic techniques to help identifying chemical species during plasma processing of a substrate (e.g., semiconductor wafer) using optical emission spectroscopy (OES). More particularly, the technology described herein uses topographic techniques to spatially resolves emissions and absorptions in at least two-dimension space above the substrate during the plasma processing (e.g., etching) of the substrate. With some implementations utilize optical detectors positioned along multiple axes (e.g., two or more) to receive incident incoming optical spectra from the plasma chamber during the plasma processing (e.g., etching) of the substrate. Because of the multi-axes arrangement, the incident incoming optical spectra form an intersecting grid.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 26, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Taejoon Han, Daniel Morvay, Mirko Vukovic
  • Publication number: 20180252650
    Abstract: Described herein are technologies to facilitate computed tomographic techniques to help identifying chemical species during plasma processing of a substrate (e.g., semiconductor wafer) using optical emission spectroscopy (OES). More particularly, the technology described herein uses topographic techniques to spatially resolves emissions and absorptions in at least two-dimension space above the substrate during the plasma processing (e.g., etching) of the substrate. With some implementations utilize optical detectors positioned along multiple axes (e.g., two or more) to receive incident incoming optical spectra from the plasma chamber during the plasma processing (e.g., etching) of the substrate. Because of the multi-axes arrangement, the incident incoming optical spectra form an intersecting grid.
    Type: Application
    Filed: March 2, 2017
    Publication date: September 6, 2018
    Inventors: Daniel Morvay, Taejoon Han, Mirko Vukovic
  • Publication number: 20180144078
    Abstract: Described herein are technologies to facilitate the generation and presentation of a map of an attribute of a substrate, such as a semiconductor wafer. Using the data of measured attribute (e.g., thickness, temperature, etc.) of a substrate, one or more of the described implementations generate data of non-measured (i.e., calculated) attributes to complete a map of the substrate using model parameters and a correlations model, such as a squared exponential Gaussian process model.
    Type: Application
    Filed: April 11, 2017
    Publication date: May 24, 2018
    Inventors: Daniel Morvay, Taejoon Han
  • Patent number: 9401263
    Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: July 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Gabriel Padron Wells, Jack Chao-Hsu Chang, Mingmei Wang, Taejoon Han
  • Publication number: 20160049495
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Applicants: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina TREVINO, Yuan-Hung LIU, Gabriel Padron WELLS, Xing ZHANG, Hoong Shing WONG, Chang Ho MAENG, Taejoon HAN, Gowri KAMARTHY, Isabelle ORAIN, Ganesh UPADHYAYA
  • Patent number: 9252238
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 2, 2016
    Assignees: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina Trevino, Yuan-Hung Liu, Gabriel Padron Wells, Xing Zhang, Hoong Shing Wong, Chang Ho Maeng, Taejoon Han, Gowri Kamarthy, Isabelle Orain, Ganesh Upadhyaya
  • Patent number: 9147680
    Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
  • Patent number: 9040380
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xiang Hu, Jin Ping Liu, Jill Hildreth, Taejoon Han
  • Patent number: 9034767
    Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiang Hu, Dae-Han Choi, Dae Geun Yang, Taejoon Han, Andy Wei
  • Publication number: 20150132962
    Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang HU, Dae-Han CHOI, Dae Geun YANG, Taejoon HAN, Andy WEI
  • Publication number: 20150076111
    Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang HU, Gabriel PADRON WELLS, Jack Chao-Hsu CHANG, Mingmei WANG, Taejoon HAN
  • Publication number: 20150069515
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Xiang Hu, Jin Ping Liu, Jill Hildreth, Taejoon Han
  • Patent number: 8940641
    Abstract: Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask overlying the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Xiang Hu, Taejoon Han, Hui Peng Koh
  • Publication number: 20150021694
    Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
  • Publication number: 20150024584
    Abstract: Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Gabriel Padron Wells, Yuan-Hung Liu, Kristina Trevino, Chang Ho Maeng, Taejoon Han
  • Patent number: 8912633
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 16, 2014
    Assignee: Lam Research Corporation
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Publication number: 20130001754
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Application
    Filed: September 7, 2012
    Publication date: January 3, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Patent number: 8283255
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: October 9, 2012
    Assignee: Lam Research Corporation
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Patent number: 8124516
    Abstract: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: February 28, 2012
    Assignee: Lam Research Corporation
    Inventors: Sean S. Kang, Sang Jun Cho, Tom Choi, Taejoon Han