Abstract: Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone.

Abstract: A plasma processing chamber is provided which provides improved wafer area pressure control. The plasma processing chamber is a vacuum chamber with a device connected for generating and sustaining a plasma. Part of this device would be an etchant gas source and an exhaust port. A confinement ring defines an area above a wafer. The wafer area pressure is dependent on the pressure drop across the confinement ring. The confinement ring is part of a wafer area pressure control device that provides wafer area pressure control range greater than 100%. Such a wafer area pressure control device may be three adjustable confinement rings and a confinement block on a holder that may be used to provide the desired wafer area pressure control.

Abstract: Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone.

Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

Abstract: Laser scanning apparatus and method using diffractive optical elements are disclosed. In one embodiment, an apparatus includes a radiation source to generate a radiation beam with an intensity profile and a wavelength capable of heating a region of a substrate, a beam shaping device based on a diffractive optical element (DOE) to transform the radiation beam to a particular shape with a particular intensity profile to illuminate the region and a state adapted to support the substrate. In another aspect, a method includes generating from a radiation source a radiation beam with an intensity profile and a wavelength capable of heating a region of a substrate transforming a shape of the radiation beam with the intensity profile to a particular shape of the radiation beam with a particular intensity profile through processing the radiation beam in a beam shaping device based on a diffractive optical element (DOE).

Abstract: In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer adhering to an etched surface of the opening and to exposed pores, and a conductive material filling the opening.

Abstract: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.

Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.

Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.

Abstract: A method for controlling a photoresist etch step in a plasma processing chamber is disclosed. The photoresist etch step being configured to etch back a photoresist layer deposited on a substrate surface to a thinner photoresist layer having predefined photoresist thickness. The method includes etching the photoresist layer using a plasma etch process and detecting interference patterns coming from the photoresist layer. The method further includes terminating the photoresist etch step when an analysis of the interference patterns indicates that the predefined photoresist thickness is achieved, whereby the predefined photoresist thickness is greater than zero.

Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.

Abstract: A plasma processing chamber is provided which provides improved wafer area pressure control. The plasma processing chamber is a vacuum chamber with a device connected for generating and sustaining a plasma. Part of this device would be an etchant gas source and an exhaust port. A confinement ring defines an area above a wafer. The wafer area pressure is dependent on the pressure drop across the confinement ring. The confinement ring is part of a wafer area pressure control device that provides wafer area pressure control range greater than 100%. Such a wafer area pressure control device may be three adjustable confinement rings and a confinement block on a holder that may be used to provide the desired wafer area pressure control.

Abstract: A plasma processing chamber is provided which provides improved wafer area pressure control. The plasma processing chamber is a vacuum chamber with a device connected for generating and sustaining a plasma. Part of this device would be an etchant gas source and an exhaust port. A confinement ring defines an area above a wafer. The wafer area pressure is dependent on the pressure drop across the confinement ring. The confinement ring is part of a wafer area pressure control device that provides wafer area pressure control range greater than 100%. Such a wafer area pressure control device may be three adjustable confinement rings and a confinement block on a holder that may be used to provide the desired wafer area pressure control.

Abstract: A method for controlling a photoresist etch step in a plasma processing chamber is disclosed. The photoresist etch step being configured to etch back a photoresist layer deposited on a substrate surface to a thinner photoresist layer having predefined photoresist thickness. The method includes etching the photoresist layer using a plasma etch process and detecting interference patterns coming from the photoresist layer. The method further includes terminating the photoresist etch step when an analysis of the interference patterns indicates that the predefined photoresist thickness is achieved, whereby the predefined photoresist thickness is greater than zero.

Abstract: A plasma processing chamber is provided which provides improved wafer area pressure control. The plasma processing chamber is a vacuum chamber with a device connected for generating and sustaining a plasma. Part of this device would be an etchant gas source and an exhaust port. A confinement ring defines an area above a wafer. The wafer area pressure is dependent on the pressure drop across the confinement ring. The confinement ring is part of a wafer area pressure control device that provides wafer area pressure control range greater than 100%. Such a wafer area pressure control device may be three adjustable confinement rings and a confinement block on a holder that may be used to provide the desired wafer area pressure control.

Abstract: A plasma processing chamber is provided which provides improved wafer area pressure control. The plasma processing chamber is a vacuum chamber with a device connected for generating and sustaining a plasma. Part of this device would be an etchant gas source and an exhaust port. A confinement ring defines an area above a wafer. The wafer area pressure is dependent on the pressure drop across the confinement ring. The confinement ring is part of a wafer area pressure control device that provides wafer area pressure control range greater than 100%. Such a wafer area pressure control device may be three adjustable confinement rings and a confinement block on a holder that may be used to provide the desired wafer area pressure control.