Abstract: The present specification relates to an electrode coating apparatus and an electrode coating method that include a turbulent flow generator to uniformize a distribution of a velocity of a coating material transferred from a supply tank to an injection port of a slot die.

Abstract: An image sensor may include a substrate including first and second surfaces opposite each other, a plurality of photoelectric conversion devices isolated from direct contact with each other within the substrate, a first trench configured to extend into an interior of the substrate from the first surface of the substrate and between adjacent photoelectric conversion devices of the plurality of photoelectric conversion devices, a first supporter within the first trench, and a first isolation layer at least partially covering both sidewalls of the first supporter within the first trench, wherein a lower surface of the first supporter is coplanar with the first surface of the substrate.

Abstract: A semiconductor image sensor includes a substrate and an isolation insulating pattern having a trench therein, on the substrate. A lower transparent electrode is provided within the trench. This lower transparent electrode includes a first layer and a different second layer on the first layer. An organic photoelectric layer is provided on the lower transparent electrode, and an upper transparent electrode is provided on the organic photoelectric layer. The first layer may contact a bottom and a side surface of the trench, and may have a seam therein, which is at least partially filled by a portion of the second layer. The first layer may have a higher light transmission efficiency relative to the second layer and a lower electrical resistance relative to the second layer.

Abstract: Image sensors with improved performance and a higher degree of integration are provided. The image sensors include a substrate including a first surface and a second surface opposite to each other, a first organic photoelectric conversion layer on the first surface of the substrate, a first penetration via connected to the first organic photoelectric conversion layer and extending through the substrate, a first floating diffusion region in the substrate adjacent to the second surface of the substrate, and a first transistor structure on the second surface of the substrate, wherein the first transistor structure includes a semiconductor layer configured to connect the first penetration via and the first floating diffusion region, a gate electrode on the semiconductor layer, and a gate dielectric film between the semiconductor layer and the gate electrode.

Abstract: Image sensors with improved performance and a higher degree of integration are provided. The image sensors include a substrate including a first surface and a second surface opposite to each other, a first organic photoelectric conversion layer on the first surface of the substrate, a first penetration via connected to the first organic photoelectric conversion layer and extending through the substrate, a first floating diffusion region in the substrate adjacent to the second surface of the substrate, and a first transistor structure on the second surface of the substrate, wherein the first transistor structure includes a semiconductor layer configured to connect the first penetration via and the first floating diffusion region, a gate electrode on the semiconductor layer, and a gate dielectric film between the semiconductor layer and the gate electrode.

Abstract: An image sensor may include a substrate including first and second surfaces opposite each other, a plurality of photoelectric conversion devices isolated from direct contact with each other within the substrate, a first trench configured to extend into an interior of the substrate from the first surface of the substrate and between adjacent photoelectric conversion devices of the plurality of photoelectric conversion devices, a first supporter within the first trench, and a first isolation layer at least partially covering both sidewalls of the first supporter within the first trench, wherein a lower surface of the first supporter is coplanar with the first surface of the substrate.

Abstract: A semiconductor image sensor includes a substrate and an isolation insulating pattern having a trench therein, on the substrate. A lower transparent electrode is provided within the trench. This lower transparent electrode includes a first layer and a different second layer on the first layer. An organic photoelectric layer is provided on the lower transparent electrode, and an upper transparent electrode is provided on the organic photoelectric layer. The first layer may contact a bottom and a side surface of the trench, and may have a seam therein, which is at least partially filled by a portion of the second layer. The first layer may have a higher light transmission efficiency relative to the second layer and a lower electrical resistance relative to the second layer.

Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

Abstract: An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

Abstract: A semiconductor device including a MOS transistor is provided. The semiconductor device may include a first MOS transistor including first source/drain regions, a first semiconductor layer between the first source/drain regions, a first gate electrode structure, and a first gate dielectric structure; and a second MOS transistor including second source/drain regions, a second semiconductor layer between the second source/drain regions, a second gate electrode structure, and a second gate dielectric structure. The first gate dielectric structure and the second gate dielectric structure include a first common dielectric structure; the first gate dielectric structure includes a first upper dielectric on the first common dielectric structure; the second gate dielectric structure includes the first upper dielectric and a second upper dielectric; and one of the first upper dielectric and the second upper dielectric is a material forming a dipole layer.

Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

Abstract: An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

Abstract: A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.

Abstract: A semiconductor device is provided. An active fin protrudes from a substrate. A gate structure is formed on the substrate and the active fin. The gate structure extends in a first direction. The gate structure crosses a first region of the active fin in a second direction. A first epitaxial layer is formed on a second region of the active fin. The second region of the active fin is not covered with the gate structure. A second epitaxial layer is formed on the first epitaxial layer, the second epitaxial layer including an impurity. The first epitaxial layer includes a blocking material. The blocking material of the first epitaxial layer prevents the impurity of the second epitaxial layer from passing through the first epitaxial layer to block diffusion of the impurity to a channel region formed in the first region of the active fin.

Abstract: A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.

Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.