Patents by Inventor Tae-Kyun Kim

Tae-Kyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140334
    Abstract: A semiconductor device includes a precharge pulse generation circuit configured to generate a first precharge pulse and a second precharge pulse, based on a column pulse generated when a column operation including a write operation and a read operation is performed. The semiconductor device also includes an input/output switching signal generation circuit configured to generate an input/output switching signal for connecting a first input/output line pair and a second input/output line pair to each other, based on the first precharge pulse and the second precharge pulse in a test mode.
    Type: Application
    Filed: February 15, 2024
    Publication date: May 1, 2025
    Applicant: SK hynix Inc.
    Inventors: Dong Yoon KA, Tae Kyun KIM
  • Patent number: 12275071
    Abstract: A cutting insert according to an embodiment of the present invention is a double-sided cutting insert comprising an upper surface, a lower surface, a side surface, a cutting edge, and a mounting hole penetrating the upper surface and the lower surface, in which the upper surface is provided with a single upper surface boss portion that surrounds the mounting hole and is flat, the cutting edge includes a main cutting edge, a corner cutting edge extending from the main cutting edge, a sub-cutting edge extending from the corner cutting edge, and a side portion extending from the sub-cutting edge, a first main cutting edge flank surface extending from the main cutting edge forms an acute angle with an extension line of the upper surface boss portion, a sub-cutting edge chip breaker surface extending from the sub-cutting edge is at a gradually increasing angle with the extension line of the upper surface boss portion, as the sub-cutting edge chip breaker surface is distanced away from the corner cutting edge, and
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 15, 2025
    Assignee: KORLOY INC.
    Inventors: Nam Seon Lee, Ki Chan Nam, Tae Kyun Kim, Young Heum Kim
  • Patent number: 12276709
    Abstract: A metal detecting system using search-coil type sensor includes sensor modules that detect respective objects which move around the corresponding sensor modules, each sensor module having one or more sensors that include respective housings having respective inner spaces, respective cores formed to be inserted into the inner spaces of the housings, and respective coils which are each wound around a portion of an outer circumferential surface of each of the housings, the portion corresponding to a position of each of the cores; imaging units that image the respective objects that move around the corresponding sensor modules and image respective persons possessing the respective objects; impedance matching units that are connected to a plurality of the sensor modules, respectively, and perform impedance matching; and amplifiers that are connected to the impedance matching units, respectively, and amplify a fine current and voltage generated during approach of the objects to the sensor modules.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 15, 2025
    Inventors: Jae Hun Choi, Tae Kyun Kim
  • Publication number: 20250113994
    Abstract: A photorefraction vision screening device for examining visual diseases by performing pupil detection and refraction test of the eye includes a measurement light irradiator configured to irradiate measurement light to an eye to be examined; a measurement light controller configured to control light-emitting elements of the measurement light irradiator; an image detector configured to detect an image formed on the retina of the eye to be examined by the measurement light having been irradiated from the light-emitting elements of the measurement light irradiator and having passed through the pupil of the eye to be examined; and a calculation part configured to calculate refractive power of the eye to be examined based on the image of the measurement light detected by the image detector.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 10, 2025
    Inventors: Jae Hyuk LEE, Kang Min KIM, Sunhyung JO, Jong Min LIM, Won Chan LEE, Tae Kyun KIM, In Seok SONG
  • Publication number: 20250012329
    Abstract: A universal joint configured to reduce the steering friction by decreasing the bending torque of a yoke. The universal joint includes a body portion formed at one end of a yoke for a shaft to be coupled thereto, a wing portion formed at the other end of the yoke for a bearing to be pressed thereinto, and a rigidity-weakening portion formed in a shape of a reduced cross-sectional area in a portion extending from the body portion to the wing portion.
    Type: Application
    Filed: November 14, 2023
    Publication date: January 9, 2025
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Jong Min Kim, Tae Kyun Kim
  • Patent number: 12191364
    Abstract: Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: January 7, 2025
    Assignee: SK hynix Inc.
    Inventors: Dong Soo Kim, Tae Kyun Kim
  • Patent number: 12181494
    Abstract: Disclosed are a probe sheet with a multi-layer contact tip and a method of manufacturing the same capable of improving the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device. According to the present invention, the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device can be improved, and since the shape of a contact surface of a contact tip is maintained the same and contact resistance is maintained in an allowable range even when a protective layer coated on the contact tip to increase durability of the contact tip is worn, test reliability of the probe card can be improved.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: December 31, 2024
    Assignee: PROTEC MEMS TECHNOLOGY INC
    Inventors: Yong Ho Cho, Tae Kyun Kim
  • Patent number: 12135227
    Abstract: A multi-measurement apparatus using a search-coil type sensor includes: sensor modules, each of which has one or more sensors including respective housings having respective inner spaces, respective cores formed to be inserted into the inner spaces of the housings, and respective coils which are each wound around a portion of an outer circumferential surface of each of the housings, the portion corresponding to a position of each of the cores; impedance matching units that are connected to a plurality of the sensors, respectively, and perform impedance matching; and amplifiers that are connected to the impedance matching units, respectively, and amplify a fine current and voltage generated during approach of objects to the sensors.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: November 5, 2024
    Inventors: Jae Hun Choi, Tae Kyun Kim
  • Patent number: 12131950
    Abstract: A semiconductor device and a method of fabricating the same are provided. According to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: October 29, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Man Yoon, Jin Hwan Jeon, Tae Kyun Kim, Jung Woo Park, Su Ock Chung, Jae Won Ha
  • Patent number: 12113107
    Abstract: A method for fabricating a semiconductor device includes: forming an insulating layer over a substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating film; etching the plug conductive layer and the insulating layer in the peripheral region by using a peri-open mask covering the cell region; trimming the peri-open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region contact each other; etching the plug conductive layer in the boundary region by using the trimmed peri-open mask; forming a peri-gate conductive layer over the entire surface of the substrate; and etching the peri-gate conductive layer by using a cell open mask.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 8, 2024
    Assignee: SK hynix Inc.
    Inventors: Dae Won Kim, Tae Kyun Kim, Dong Goo Choi
  • Patent number: 12113035
    Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: October 8, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Su Lee, Hong Sik Chae, Youn Soo Kim, Tae Kyun Kim, Youn Joung Cho
  • Patent number: 12092494
    Abstract: An apparatus for correcting non-polarity and measuring displacement of an object using a search-coil type sensor includes a plurality of sensors that include respective housings having respective inner spaces, respective cores formed to be inserted into the inner spaces of the housings, and respective coils which are each wound around a portion of an outer circumferential surface of each of the housings, the portion corresponding to a position of each of the cores. The plurality of sensors are arranged in parallel with each other. A position of a core and a coil with respect to one housing differs from a position of a core and a coil with respect to another housing. An induced magnetic field is formed due to a distance change with respect to the object containing iron (Fe).
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: September 17, 2024
    Inventors: Jae Hun Choi, Tae Kyun Kim
  • Publication number: 20240230717
    Abstract: Disclosed are a probe sheet with a multi-layer contact tip and a method of manufacturing the same capable of improving the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device. According to the present invention, the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device can be improved, and since the shape of a contact surface of a contact tip is maintained the same and contact resistance is maintained in an allowable range even when a protective layer coated on the contact tip to increase durability of the contact tip is worn, test reliability of the probe card can be improved.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 11, 2024
    Inventors: Yong Ho CHO, Tae Kyun KIM
  • Patent number: 11981658
    Abstract: Provided are aminopyridine compounds and pharmaceutically acceptable compositions thereof which exhibit inhibition activity against certain mutated forms of EGFR.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: May 14, 2024
    Assignees: Yuhan Corporation, Janssen Biotech, Inc.
    Inventors: Byoungmoon Lee, Hyunjoo Lee, Gyu Jin Lee, Su Bin Choi, Sol Park, Heejun Kim, Misong Kim, Young Ae Yoon, Kwan Hoon Hyun, Tae Kyun Kim, Jae Young Sim, Marian C. Bryan, Scott Kuduk, James Campbell Robertson
  • Publication number: 20240153133
    Abstract: The present invention relates to a hand position estimation method and system for estimating a 3-dimensional hand position for quick hand movement, on the basis of domain transfer learning from a depth image to an infrared image, the hand position estimation method comprising the steps of: processing a depth image and an infrared image for hand movement; synthesizing a depth map with the infrared image by using a hand image generator (HIG), and estimating skeletal positions of hand joints from each of the depth map and an infrared map; and calculating a 3-dimensional hand position by using the skeletal positions and the center of a hand depth image.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 9, 2024
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Woontack Woo, Gabyong Park, Tae Kyun Kim
  • Publication number: 20240121948
    Abstract: A semiconductor device and a method of fabricating the same are provided. According to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Jae Man YOON, Jin Hwan JEON, Tae Kyun KIM, Jung Woo PARK, Su Ock CHUNG, Jae Won HA
  • Publication number: 20240079355
    Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.
    Type: Application
    Filed: November 1, 2023
    Publication date: March 7, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-su LEE, Hong Sik CHAE, Youn Soo KIM, Tae Kyun KIM, Youn Joung CHO
  • Publication number: 20240079456
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench in an insulating interlayer by etching the insulating interlayer; forming a conductive layer on bottom, side, and upper surfaces of the insulating interlayer where the trench is formed, using a first deposition process, the conductive layer on the bottom surface of the trench being thicker than the conductive layer on the side surface of the trench; forming a sacrificial layer in the trench covering the conductive layer formed on the bottom surface of the trench using a second deposition process different from the first deposition process; selectively removing the conductive layer formed on the upper surface of the insulating interlayer and formed on the side surface of the trench left exposed through the sacrificial layer; and selectively removing the sacrificial layer, to form a conductive line using the conductive layer remaining on the bottom surface of the trench.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Man YOON, Jun Ki KIM, Tae Kyun KIM, Jung Woo PARK, Jae Won HA
  • Patent number: 11920034
    Abstract: Described herein is a polyamide composition (P) including specific flat glass fibres (B) with elongated shape having a non-circular cross-sectional area. The polyamide composition (P) is advantageously used for the production of molded parts. Also described herein is a method of using molded parts obtainable by molding of the polyamide composition (P) to produce mechanical parts. The molded parts are characterized by having improved fatigue resistance properties. Also described herein is a polyamide composition (P) including PA 6.6 as polyamide (A) and flat glass fibres (B).
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 5, 2024
    Assignee: BASF SE
    Inventors: Gilles Robert, Tae-Kyun Kim, Weibing Wang, Franco Speroni
  • Patent number: D1058623
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: January 21, 2025
    Inventors: Tae Kyun Kim, Nam Seon Lee, Min Seok Oh, Sang Yong Lee, Young Heum Kim