Abstract: A computed tomography (CT) apparatus according to various embodiments may include a gantry including a first rotation device, a second rotation device and a third rotation device which have a ring shape, share an axis of rotation, and are rotatable independently of one another, a plurality of first light sources provided on the first rotation device at regular intervals and configured to emit X-rays to a subject, a plurality of second light sources provided on the second rotation device at regular intervals and configured to emit X-rays to the subject, a detector provided on a region of the third rotation device and configured to detect X-rays passing through the subject, and one or more processors.

Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive spaced-apart pillar structures.

Abstract: The present disclosure relates to a method for carrying out dose delivery quality assurance for high-precision radiation treatment, in which parameters affecting a pass rate of dose delivery quality assurance can be derived through regression analysis, which is a known statistical analysis method, and a pass rate prediction model capable of predicting each parameter and the pass rate of dose delivery quality assurance can be derived, and accordingly, it can be predicted in advance whether dose delivery quality assurance will be passed according to the parameters through the above prediction model, without repeatedly carrying out dose delivery quality assurance according to a patient's treatment plan, and as a result, the efficiency of dose delivery quality assurance can be enhanced, and the time or capacity required for such quality assurance is reduced, such that radiation treatment for an actual patient can be quickly and precisely carried out.

Abstract: The present invention relates to a method of manufacturing polycrystalline silicon ingot using a crucible in which an oxygen exhaust passage is formed by single crystal or polycrystalline rods, the method including the steps of: manufacturing the single crystal or polycrystalline silicon rods each having the shape of a quadrilateral pillar; putting the single crystal or polycrystalline quadrilateral pillar-shaped silicon rods into the crucible in such a manner as to be arranged close to one another along the inner peripheral surface of the crucible to thus form a space portion inside the single crystal or polycrystalline silicon rods, into which silicon chunks are put, and the oxygen exhaust passages between the inner peripheral surface of the crucible and the respective surfaces of the single crystal or polycrystalline silicon rods oriented toward the inner peripheral surface of the crucible; putting the silicon chunks into the space portion of the crucible; and melting and crystallizing the silicon chunks.

Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.

Abstract: A computed tomography (CT) apparatus includes a gantry including a rotation device which has a ring shape and is rotatable about an axis of rotation, a plurality of light sources configured to emit X-rays to a subject, at least one detector provided on the rotation device and configured to detect X-rays passing through the subject, and one or more processors. The at least one processors are configured to rotate the rotation device in a first rotation direction by an angle of rotation determined based on a total number of the plurality of light sources, emit X-rays to the subject and detect X-rays passing through the subject during the rotation of the rotation device in the first rotation direction, and rotate the rotation device by the determined rotation angle in a second rotation direction.

Abstract: An imaging pixel design is provide with a photo-sensor block structure that facilitates dynamic control of well capacity in the photodiode region (i.e., a “well capacity adjustment (WCA) gate photo-sensor block”). The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.

Abstract: A trench-gate source-follower (TGSF) transistor is described, such as for integration with image sensor pixels. The TGSF transistor is at least partially built into a trench etched into a substrate. A contiguous doped region is implanted around the inner walls of the trench to form a buried-trench current channel. A trench-gate is formed to have at least a buried portion that fills the volume of the trench. A gate oxide layer can be disposed between the buried portion of the trench-gate and the buried-trench current channel. Drain and source regions are formed on either end of the trench-gate. Activating the trench-gate causes current to flow between the drain and source regions via the buried-trench current channel around the buried portion of the trench-gate. The geometry of the buried-trench current channel can effectively increase the width of the active region of the source-follower transistor without increasing its physical layout width.

Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.

Abstract: Techniques are described for implementing a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture, such as for reducing noise in low-light application contexts. The split-SEL CIS pixel physical architecture can include a pixel block with one or more photodiodes. Above the photodiodes, there can be: a first oxide diffusion region with a reset block and a gain block disposed thereon; and a second oxide diffusion region with a select block disposed thereon. Below the photodiodes, there can be a third oxide diffusion region with a source follower (SF) block (e.g., a square-gate SF transistor) disposed thereon. A trace can be routed through the set of photodiodes to couple the source of the SF block with the select block. The architecture permits an appreciable increase in the physical gate length and/or other features.

Abstract: A computed tomography (CT) apparatus according to various embodiments may include a gantry including a first rotation device, a second rotation device and a third rotation device which have a ring shape, share an axis of rotation, and are rotatable independently of one another, a plurality of first light sources provided on the first rotation device at regular intervals and configured to emit X-rays to a subject, a plurality of second light sources provided on the second rotation device at regular intervals and configured to emit X-rays to the subject, a detector provided on a region of the third rotation device and configured to detect X-rays passing through the subject, and one or more processors.

Abstract: A computed tomography (CT) apparatus includes a gantry with a first rotation device and a second rotation device, a plurality of light sources configured to emit X-rays to a subject, a detector configured to detect X-rays passing through the subject, and one or more processors. The one or more processors may be configured to rotate the first rotation device in a first rotation direction by an angle of rotation determined based on a total number of the plurality of light sources, emit X-rays to the subject by using at least one of the plurality of light sources and detect X-rays passing through the subject during the rotation of the first rotation device in the first rotation direction, and rotate the first rotation device by the determined angle of rotation in a second rotation direction.

Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.

Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.

Abstract: A saddle-gate source follower transistor is described, such as for integration with in-pixel circuitry of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The saddle-gate source-follower transistor structure can include a channel region having a three-dimensional geometry defined on its axial sides by trenches. A gate oxide layer is formed over the top and axial sides of the channel region, and a saddle-gate structure is formed on the gate oxide layer. As such, the saddle-gate structure includes a seat portion extending over the top of the channel region, and first and second fender portions extending over the first and second axial sides of the channel region, such that the first and second fender portions are buried below an upper surface of the semiconductor substrate (e.g., buried into trenches formed in side isolation regions).

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.