Patents by Inventor TaeWoo Kang
TaeWoo Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120193132Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.Type: ApplicationFiled: April 6, 2012Publication date: August 2, 2012Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
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Publication number: 20120187559Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: STATS CHIPPAC, LTD.Inventors: SungWon Cho, TaeWoo Kang
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Patent number: 8216930Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: December 21, 2009Date of Patent: July 10, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 8211746Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed; and attaching a base substrate connector to the base substrate directly below the leadframe pillar.Type: GrantFiled: May 27, 2011Date of Patent: July 3, 2012Assignee: Stats Chippac Ltd.Inventors: Jong-Woo Ha, TaeWoo Kang, DongSoo Moon
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Publication number: 20120133043Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: ApplicationFiled: February 6, 2012Publication date: May 31, 2012Applicant: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Patent number: 8178392Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.Type: GrantFiled: May 18, 2007Date of Patent: May 15, 2012Assignee: Stats Chippac Ltd.Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
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Patent number: 8173536Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.Type: GrantFiled: November 2, 2009Date of Patent: May 8, 2012Assignee: STATS ChipPAC, Ltd.Inventors: SungWon Cho, TaeWoo Kang
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Patent number: 8129841Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: GrantFiled: November 24, 2009Date of Patent: March 6, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Publication number: 20110227206Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed; and attaching a base substrate connector to the base substrate directly below the leadframe pillar.Type: ApplicationFiled: May 27, 2011Publication date: September 22, 2011Inventors: Jong-Woo Ha, TaeWoo Kang, DongSoo Moon
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Patent number: 8018052Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.Type: GrantFiled: June 29, 2007Date of Patent: September 13, 2011Assignee: Stats Chippac Ltd.Inventors: KyungOe Kim, Taewoo Kang, HyunSu Shin
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Patent number: 7951643Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.Type: GrantFiled: November 29, 2008Date of Patent: May 31, 2011Assignee: Stats Chippac Ltd.Inventors: Jong-Woo Ha, TaeWoo Kang, DongSoo Moon
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Publication number: 20110101518Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: STATS CHIPPAC, LTD.Inventors: SungWon Cho, TaeWoo Kang
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Patent number: 7875495Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.Type: GrantFiled: September 30, 2009Date of Patent: January 25, 2011Assignee: STATS ChipPAC, Ltd.Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
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Publication number: 20100133665Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.Type: ApplicationFiled: November 29, 2008Publication date: June 3, 2010Inventors: Jong-Woo Ha, TaeWoo Kang, DongSoo Moon
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Publication number: 20100099222Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: ApplicationFiled: December 21, 2009Publication date: April 22, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Publication number: 20100065966Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.Type: ApplicationFiled: November 24, 2009Publication date: March 18, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
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Patent number: 7659633Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.Type: GrantFiled: December 14, 2006Date of Patent: February 9, 2010Assignee: STATS ChipPAC, Ltd.Inventors: Rajendra D. Pendse, KyungOe Kim, Taewoo Kang
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Publication number: 20100022050Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.Type: ApplicationFiled: September 30, 2009Publication date: January 28, 2010Applicant: STATS CHIPPAC, LTD.Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
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Patent number: 7615865Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.Type: GrantFiled: May 21, 2007Date of Patent: November 10, 2009Assignee: STATS ChipPAC, Ltd.Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
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Publication number: 20090236731Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Inventors: Seong Bo Shim, TaeWoo Kang, Yong Hee Kang