Patents by Inventor TaeWoo Kang

TaeWoo Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090001545
    Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: KyungOe Kim, Taewoo Kang, HyunSu Shin
  • Publication number: 20080293232
    Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 27, 2008
    Applicant: STATS CHIPPAC, LTD.
    Inventors: TaeWoo KANG, YoRim LEE, TaeKeun LEE
  • Publication number: 20080283998
    Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 20, 2008
    Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
  • Publication number: 20070241464
    Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.
    Type: Application
    Filed: December 14, 2006
    Publication date: October 18, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Rajendra Pendse, KyungOe Kim, Taewoo Kang
  • Publication number: 20070105277
    Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.
    Type: Application
    Filed: December 14, 2006
    Publication date: May 10, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Rajendra Pendse, KyungOe Kim, Taewoo Kang