Abstract: An optical sensor including a pixel matrix and an opaque layer is provided. The pixel matrix includes a plurality of unblocked pixels, a first pixel and a second pixel, which is arranged at a side of the first pixel in a row direction of the pixel matrix. The opaque layer covers upon a first region, which is a part of the first pixel, and upon a second region, which is a part of the second pixel, but does not cover upon the unblocked pixels, wherein the first region and the second region are symmetrically arranged in the row direction, and uncovered regions of the first pixel and the second pixel are arranged to be larger at a pixel edge than at a pixel center in a column direction of the pixel matrix.

Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.

Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.

Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.

Abstract: The present disclosure relates to methods of treating or preventing cancer (e.g., advanced solid cancer) using Compound No. 1 or Compound No. 2: or a pharmaceutically acceptable salt thereof. The present disclosure also relates to pharmaceutical compositions and pharmaceutical kits suitable for the treatment or prevention.

Abstract: An optical module including a light source and an optical sensor is provided. The optical sensor includes a pixel matrix and an opaque layer. The pixel matrix includes a plurality of unblocked pixels, a plurality of first pixels and a plurality of second pixels. The opaque layer covers upon a first region, which is a part of each first pixel, and upon a second region, which is a part of each second pixel, but does not cover upon the unblocked pixels, wherein the first region and the second region are symmetrically arranged in a first direction, and uncovered regions of the first pixels and the second pixels are arranged to be larger at a pixel edge than at a pixel center.

Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: An external neurostimulator includes a housing including a base housing and a top housing, a power source, a pulse generator, and a first and second series of spring-loaded pins electrically coupled to the pulse generator. The top housing includes a central portion, a first side door hingedly coupled to a first side of the central portion, and a second side door hingedly coupled to a second side of the central portion. Each of the first side door and the second side door include a channel formed thereon that is configured to directly receive a proximal end portion of an implantable lead. Each channel includes a series of longitudinally spaced-apart openings formed on the first side door and the second side door, respectively. The first and second series of spring-loaded pins extend through the series of longitudinally spaced-apart openings of the channel on the first and second side doors, respectively.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).

Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.

Abstract: A surgical navigation method includes selecting one or more two-dimensional images from a three-dimensional image. The method further includes adjusting a portion of the two-dimensional images along a viewing direction. The method also includes superimposing the portion of the two-dimensional images along the viewing direction to form a two-dimensional superimposed image. The method further incudes guiding movement of a virtual surgical instrument into the two-dimensional superimposed image.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

Abstract: A method for facilitating a flow from a sending end to a receiving end by multi-path transmission is introduced. The method is applied to a network controller of a software-defined network. The software-defined network includes a plurality of switches. The switches execute packet forwarding from the sending end to the receiving end. The method includes: executing, by the network controller, operations, so as for a flow from the sending end to reach the receiving end by multi-path transmission using a plurality of network paths, so as to enable the multi-path transmission to be transparent to the sending end and the receiving end. The network controller is, according to the method, configured to facilitate a transmission mechanism for multi-path stochastic switching or a transmission mechanism for multi-path stochastic switching with network coding, so as to enable multi-path transmission of the packets in one single flow and thus enhance transmission performance.