Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.

Abstract: An optical device is provided. The optical device includes a substrate, a first optical layer; a high k layer, and a second optical layer. The first optical layer is disposed on the substrate. The first optical layer comprises a top surface, a first sidewall, and a second side-wall opposite thereto. The high k layer is disposed on the top surface of the first optical layer. The second optical layer is disposed on the high k layer. The second optical layer includes a top surface, a third sidewall, and a fourth sidewall opposite thereto. The first sidewall of the first optical layer is misaligned with the third sidewall of the second optical layer. The second sidewall of the first optical layer is coplanar with the fourth sidewall of the second optical layer.

Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming fins from a substrate, forming a dummy gate stack over portions of the fins, forming epitaxial source/drain regions adjacent the dummy gate stack, depositing a first inter-layer dielectric (ILD) over the epitaxial source/drain region, replacing the dummy gate stack with a first gate stack, forming a trench through the first gate stack and into an isolation region under the first gate stack, and forming a dielectric layer in the trench by an atomic layer deposition process, wherein the dielectric layer is non-conformal.

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Abstract: An optical device is provided. The optical device includes a ring waveguide and a bus waveguide. The ring waveguide includes a coupling region. The bus waveguide is disposed adjacent to and spaced apart from the coupling region of the ring waveguide. The bus waveguide includes a coupling structure corresponding to the coupling region.

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: A method includes forming a first dummy gate stack on a protruding semiconductor fin, etching the first dummy gate stack to form a trench, extending the trench downwardly to penetrate through a portion of the protruding semiconductor fin, and filling the trench with a dielectric material to form a fin isolation region. A seam is formed in the fin isolation region, and the seam extends to a level lower than a top surface level of the protruding semiconductor fin. The seam has a top width smaller than about 1 nm. A second dummy gate stack on the protruding semiconductor fin is replaced with a replacement gate stack.

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes an isolation structure formed over a semiconductor substrate. A first fin structure and a second fin structure extend from the semiconductor substrate and protrude above the isolation structure. A first gate structure is formed across the first fin structure and a second gate structure is formed across the second fin structure. A gate isolation structure is formed between the first fin structure and the second fin structure and separates the first gate structure from the second gate structure. The gate isolation structure includes a bowl-shaped insulating layer that has a first convex sidewall surface adjacent to the first gate structure and a second convex sidewall surface adjacent to the second gate structure.

Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.

Abstract: A semiconductor structure includes a first gate stack across a first semiconductor fin structure, a second gate stack across a second semiconductor fin structure, a dielectric fin structure between the first semiconductor fin structure and the second semiconductor fin structure, and a gate cut isolation structure over the dielectric fin structure and between the first gate stack and the second gate stack. The gate cut isolation structure includes a protection layer and a fill layer over the protection layer, and the protection layer and the fill layer are made of different materials.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.

Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.