Patents by Inventor Tai-I Yang

Tai-I Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002709
    Abstract: The present disclosure provides an interconnect structure, including a first metal line, a second metal line spaced away from the first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, wherein a shortest distance between the second portion and the second metal line is in a range from 50 Angstrom to 200 Angstrom, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, the entire first portion and the entire second portion are under a coverage of a vertical projection area of the third portion, a first layer, and a second layer over the first layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Wei Liu, Wei-Chen Chu, Chia-Tien Wu, Tai-I Yang
  • Patent number: 11988625
    Abstract: A capacitive biosensor is provided. The capacitive biosensor includes: a transistor, an interconnect structure on the transistor, and a passivation layer on the interconnect structure. The interconnect structure includes a first metal structure on the transistor, a second metal structure on the first metal structure, and a third metal structure on the second metal structure. The third metal structure includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The passivation has an opening exposing a portion of the third metal structure. The capacitive biosensor further includes a sensing region on the interconnect structure. The sensing region includes a first sensing electrode and a second sensing electrode. The first sensing electrode is formed of the third conductive layer, and the second sensing electrode is disposed on the passivation layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 21, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Ping Chang, Chien-Hui Li, Chien-Hsun Wu, Tai-I Yang, Yung-Hsiang Chen
  • Patent number: 11940388
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2024
    Assignee: IXENSOR CO., LTD.
    Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
  • Publication number: 20240085803
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11860550
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11842962
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Publication number: 20230369114
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20230369096
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Tai-I YANG, Wei-Chen CHU, Yung-Chih WANG, Chia-Tien WU, Hsin-Ping CHEN, Shau-Lin SHUE
  • Patent number: 11784627
    Abstract: A Lamb wave resonator includes a piezoelectric material layer, a first finger electrode, a second finger electrode, at least two floating electrodes, and at least two gaps. The first finger electrode is disposed on one side of the piezoelectric material layer and includes a first main portion and first fingers. The second finger electrode is disposed on the side of the piezoelectric material layer and includes a second main portion and second fingers. The first fingers are parallel to and alternately arranged with the second fingers. The floating electrodes are disposed between each first finger and each second finger, and the gaps are disposed at two ends of each floating electrode, respectively.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: October 10, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Yu Chang, Yen-Lin Chen, Chien-Hui Li, Tai-I Yang, Yung-Hsiang Chen
  • Patent number: 11769695
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11764106
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
  • Patent number: 11640924
    Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-I Yang, Yu-Chieh Liao, Chia-Tien Wu, Hsin-Ping Chen, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20220367357
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Publication number: 20220359380
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The conductive line has a barrier region surrounding an inner portion of the conductive line, and the barrier region has a greater dopant concentration than the inner portion. The semiconductor device structure also includes a conductive via on the conductive line. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate. The dielectric layer surrounds the conductive line and the conductive via.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-I YANG, Wei-Chen CHU, Yung-Hsu WU, Chung-Ju LEE
  • Patent number: 11495539
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Publication number: 20220350262
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I YANG, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11435224
    Abstract: The present disclosure relates to a stringed instrument resonance analysis device which uses a scientific detection method to evaluate the resonance effect of stringed instrument, wherein the stringed instrument resonance analysis device has a cabinet, a holder, a resonant sounder, a sonic generator, at least one sonic collector and a spectrum analyzer. The cabinet forms an accommodating space therein. The holder a holder is disposed in the accommodating space and used to fix and hold the stringed instrument. The resonant sounder is disposed in the accommodating space and fixed and clamped to a bridge on a loudspeaker box of the stringed instrument. The sonic generator is connected to the resonant sounder. The sonic collector is disposed in the accommodating space and adjacent to the loudspeaker box of the stringed instrument. The spectrum analyzer is connected to the at least one sonic collector.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 6, 2022
    Assignee: Fon Da Tech Co., Ltd.
    Inventors: Tai-I Yang, Dai-Ting Chung, Chien-Hung Tu, Jen-Yu Chung
  • Patent number: 11422475
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Publication number: 20220247378
    Abstract: A Lamb wave resonator includes a piezoelectric material layer, a first finger electrode, a second finger electrode, at least two floating electrodes, and at least two gaps. The first finger electrode is disposed on one side of the piezoelectric material layer and includes a first main portion and first fingers. The second finger electrode is disposed on the side of the piezoelectric material layer and includes a second main portion and second fingers. The first fingers are parallel to and alternately arranged with the second fingers. The floating electrodes are disposed between each first finger and each second finger, and the gaps are disposed at two ends of each floating electrode, respectively.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 4, 2022
    Inventors: Chin-Yu Chang, Yen-Lin Chen, Chien-Hui Li, Tai-I Yang, Yung-Hsiang Chen
  • Patent number: 11404367
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu, Chung-Ju Lee