Abstract: An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract: Embodiments of mechanisms of an optical inspection system for inspecting an object are provided. The optical inspection system includes a light source emitting a coherent beam having a first width, and a beam expander increasing the first width to a second width. The optical inspection system also includes an polaroid module adjacent to the beam expander and polarizing the coherent beam. The object generates an inspection beam with an interference pattern by reflecting the polarized coherent beam. The optical inspection system further includes an image module capturing the inspection beam.

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract: The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.