Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer. The interconnect is adjacent a sidewall of a dielectric, such that an air gap is between the interconnect and the sidewall of the dielectric. A protective barrier is over the interconnect and the air gap, and is over and in direct physical contact with a top surface of the dielectric. The interconnect metal plug surrounded by the second metal layer is less susceptible to damage than an interconnect metal plug that is not surrounded by a second metal layer. The protective barrier in direct physical contact with the dielectric reduces parasitic capacitance, which reduces an RC delay of the semiconductor arrangement, as compared to a semiconductor arrangement that does not have a protective barrier in direct physical contact with a dielectric.

Abstract: An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer. The interconnect is adjacent a sidewall of a dielectric, such that an air gap is between the interconnect and the sidewall of the dielectric. A protective barrier is over the interconnect and the air gap, and is over and in direct physical contact with a top surface of the dielectric. The interconnect metal plug surrounded by the second metal layer is less susceptible to damage than an interconnect metal plug that is not surrounded by a second metal layer. The protective barrier in direct physical contact with the dielectric reduces parasitic capacitance, which reduces an RC delay of the semiconductor arrangement, as compared to a semiconductor arrangement that does not have a protective barrier in direct physical contact with a dielectric.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.

Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.

Abstract: A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line.

Abstract: The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material.

Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract: A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride.

Abstract: An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract: An apparatus may include a vessel adapted to contain an organic solvent and a dehydration apparatus coupled with the vessel. The dehydration apparatus may be adapted to remove water from the organic solvent. The apparatus may further include a water content monitor coupled to the dehydration apparatus and the vessel, in which the water content monitor is adapted to determine a water content of the organic solvent. The apparatus may further include a wafer handler adapted to transfer at least one semiconductor wafer including a MEMS device into the vessel.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer. The interconnect is adjacent a sidewall of a dielectric, such that an air gap is between the interconnect and the sidewall of the dielectric. A protective barrier is over the interconnect and the air gap, and is over and in direct physical contact with a top surface of the dielectric. The interconnect metal plug surrounded by the second metal layer is less susceptible to damage than an interconnect metal plug that is not surrounded by a second metal layer. The protective barrier in direct physical contact with the dielectric reduces parasitic capacitance, which reduces an RC delay of the semiconductor arrangement, as compared to a semiconductor arrangement that does not have a protective barrier in direct physical contact with a dielectric.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Abstract: Methods and apparatus for MEMS release are disclosed. A method is described including providing a substrate including at least one MEMS device supported by a sacrificial layer; performing an etch in solution to remove the sacrificial layer from at least one MEMS device; immersing the substrate including the at least one MEMS device in an organic solvent; and while the substrate is immersed in the organic solvent, removing water from the organic solvent until the water remaining in the organic solvent is less than a predetermined threshold. An apparatus is disclosed for performing the methods. Additional alternative methods are disclosed.

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.