Abstract: A touch panel including a carrier component, a plurality of first electrode series and a plurality of second electrode series is provided. Each first electrode series includes a plurality of first electrodes connected in series in a first direction. Each second electrode series includes a plurality of second electrodes connected in series in a second direction. In a unit sensing area arbitrarily selected on the touch panel, a ratio of the unit sensing area occupied by each of the first electrodes to the unit sensing area occupied by each of the second electrodes is 1:1.2 to 1:1.4, wherein a length and a width of the unit sensing area are equal to pitches of the first electrodes in the first direction and the second direction respectively.

Abstract: A sound quality testing method and system test sound quality of a network-based communication device. The method includes connecting the network-based communication device to a test host through the Internet; sending a testing signal from the test host to the sound receiving unit for generating an audio packet signal; sending the audio packet signal from the sound receiving unit to the test host through the Internet to produce a first test result; sending a test packet signal from the test host to the network-based communication device through the Internet to enable the network-based communication device to generate a speaker signal; receiving and analyzing the speaker signal by the test host to produce a second test result; and evaluating sound quality of the network-based communication device by the test host based on the first test result and the second test result.

Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.

Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.

Abstract: A gate mask is formed on a silicon substrate of a semiconductor wafer followed by etching region of the silicon substrate not covered by the gate mask to a predetermined depth. Subsequently, a silicon oxide layer is formed on the region of the silicon substrate not covered by the gate mask. A first conductive layer and a second conductive layer are formed respectively on the silicon substrate. Then, a first etching back process is performed to form a spacer consisting of the second conductive layer, the first conductive layer and the silicon oxide layer on the region of the silicon substrate below the gate mask. After the gate mask is removed, a selective etching process is performed to remove portions of both the first conductive layer and the silicon oxide layer to form the spacer into an undercut profile. Finally, a doping process and an ion implantation process are performed, respectively, to form lightly doped drains (LDDs) and a source/drain (S/D) of a vertical MOS transistor.

Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.

Abstract: A method of forming a damascene structure. A porous dielectric layer is formed over a substrate. The porous dielectric layer is patterned to form an opening that exposes a portion of the substrate. A conformal low dielectric constant layer is formed over the substrate and the exposed surface of the opening. A portion of the low dielectric constant material is removed to form spacers on the sidewalls of the porous dielectric layer. A conformal barrier layer and a conductive layer are sequentially formed over the opening. Excess conductive material and barrier material outside the opening above the dielectric layer are removed to form a damascene structure.

Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.

Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.

Abstract: A method for forming polysilicon-filled trench isolations is provided. The present method is characterized in that using nitrogen implantation to amorphize the top portion of the polysilicon filled in the trench isolation and then a nitrogen-implanted region formed in this top portion. The nitrogen-implanted region forms an oxynitride cap layer during the polysilicon oxidation. The oxynitride cap layer provides better erosive resistance to acidic solutions for stripping away photopresist layers used for several wells/Vth implantations than a silicon dioxide layer. The oxynitride cap layer also reduces the gate-to-channel fringing field because its dielectric constant is higher than that of silicon dioxide. Moreover, the nitrogen-implanted region in the top portion of the polysilicon decreases the polysilicon oxidation time so that the channel edge oxidation is reduced.

Abstract: A method of forming a shallow trench isolation (STI) structure. A pad oxide layer and a cap layer are sequentially formed over a substrate. The pad oxide layer, the cap layer and the substrate are patterned to form a trench. Oxide material is deposited into the trench to form a first oxide layer. The cap layer is removed to expose a portion of the first oxide layer. The pad oxide layer is removed. A selective liquid phase deposition is conducted to form a second oxide layer around the exposed first oxide layer.

Abstract: This invention relates to a method for filling of a shallow trench isolation, more particularly, to a method of gap filling shallow trench isolation with ozone-TEOS. A pad oxide layer is provided over the surface of a substrate. The first nitride layer is deposited overlying the pad oxide layer. A isolation trench is etched through the first nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. The second silicon nitride layer is deposited over the first nitride layer and over the thermal oxide layer within the isolation trenches. The second silicon nitride layer and the thermal oxide layer which are on the first surface of the isolation trenches are removed by using the anisotropic etching method and the semiconductor substrate is shown. Thereafter, an ozone-TEOS layer is deposited overlying the second silicon nitride layer and the semiconductor substrate and filling the isolation trenche.

Abstract: The present invention provides a method of fabricating a STI on a wafer to eliminate the common occurrence of junction leakage in the prior art. The method begins by forming a patterned hard mask on a silicon substrate. The patterned hard mask is a laminated layer comprising a pad oxide and a silicon nitride layer, and exposes a portion of the surface of the silicon substrate. The exposed portion of the silicon substrate is then dry etched to form a trench in the silicon substrate having a <100> surface and a <111> surface. Next, a portion of the pad oxide is wet etched around the STI corners of the trench to expose a portion of the top surface of the silicon substrate surrounding the periphery of the trench. A microwave-excited Kr/O2 plasma is used to oxidize both the interior surface of the trench and the exposed top surface of the silicon substrate located beneath the layer of silicon nitride surrounding the periphery of the trench at a temperature of 400° C.

Abstract: A method of making a polysilicon thin-film transistor is presented. Device characteristics are improved when a silicon dioxide capping layer is formed by an ion plating method.