Patents by Inventor Tai-Yu Chen

Tai-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282604
    Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.
    Type: Application
    Filed: February 7, 2023
    Publication date: September 7, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Tai-Yu Chen, Shih-Chin Lin, Isabella Song, Wen-Chin Tsai
  • Publication number: 20230282626
    Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.
    Type: Application
    Filed: February 2, 2023
    Publication date: September 7, 2023
    Inventors: Tai-Yu CHEN, Bo-Jiun YANG, Tsung-Yu PAN, Yin-Fa CHEN, Ta-Jen YU, Bo-Hao MA, Wen-Sung HSU, Yao-Pang HSU
  • Publication number: 20230273534
    Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 31, 2023
    Inventors: Chieh HSIEH, Tai-Yu CHEN, Cho-Ying LIN, Heng-Hsin LIU, Li-Jui CHEN, Shang-Chieh CHIEN
  • Publication number: 20230260866
    Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 17, 2023
    Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU
  • Patent number: 11728232
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: August 15, 2023
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Publication number: 20230238302
    Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Sheng-Liang Kuo, Bo-Jiun Yang
  • Patent number: 11705413
    Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 18, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Publication number: 20230205907
    Abstract: A method and a system for managing login information of a computing system during a debugging process are disclosed. The login information is composed according to a number of roles and their associated policies. Some roles have higher authorized levels to view sensitive information. To protect privacy, a technician who access the computing system will not be able to view all content of information. If this restriction prevents the technician to debug the system, the technician can request an upgrade. A new login information with a higher authorized level will be temporarily granted to the technician that allows the technician to view and access more content of information.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Kyocera Document Solutions, Inc.
    Inventor: Tai Yu CHEN
  • Publication number: 20230197667
    Abstract: A semiconductor device includes a substrate, an electronic component, a cover, a heat conduction component and a dam. The electronic component is disposed on the substrate. The cover is disposed on the substrate and covers the electronic component. The heat conduction component is disposed between the electronic component and the cover. The dam is disposed between the electronic component and the cover and surrounds the heat conduction component.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 22, 2023
    Inventors: Yu-Jin LI, Bo-Jiun YANG, Tai-Yu CHEN, Tsung-Yu PAN, Chun-Yin LIN
  • Publication number: 20230185280
    Abstract: An integrated circuit (IC) configurable to perform adaptive thermal ceiling control in a per-functional-block manner, an associated main circuit, an associated electronic device and an associated thermal control method are provided. The IC may include a plurality of hardware circuits arranged to perform operations of a first functional block, and at least one thermal control circuit. At least one temperature sensor is coupled with the first functional block to detect temperature and to generate at least one temperature sensing result of the first functional block.
    Type: Application
    Filed: November 23, 2022
    Publication date: June 15, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chih-Fu Tsai, Yu-Chia Chang, Bo-Jiun Yang, Yen-Hwei Hsieh, Shun-Yao Yang, Jia-Wei Fang, Ta-Chang Liao, Tai-Yu Chen
  • Patent number: 11662668
    Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chieh Hsieh, Tai-Yu Chen, Cho-Ying Lin, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 11647578
    Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: May 9, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yu Chen, Cho-Ying Lin, Sagar Deepak Khivsara, Hsiang Chen, Chieh Hsieh, Sheng-Kang Yu, Shang-Chieh Chien, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Zhiqiang Wu
  • Patent number: 11640930
    Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 2, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Sheng-Liang Kuo, Bo-Jiun Yang
  • Patent number: 11632849
    Abstract: A shutter is provided near the immediate focus of a lithography apparatus in order to deflect tin debris generated by a source side of the apparatus away from a scanner side of the apparatus and towards a debris collection device. The activation of the shutter is synchronized with the generation of light pulses so as not to block light from entering the scanner side.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh Hsieh, Tai-Yu Chen, Hung-Jung Hsu, Cho-Ying Lin, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 11621211
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die, a molding material, a first bonding layer, and a thermal interface material. The semiconductor die is disposed over the substrate. The molding material surrounds the semiconductor die. The first bonding layer is disposed over the semiconductor die. The thermal interface material is disposed over the molding material.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 4, 2023
    Assignee: MediaTek Inc.
    Inventors: Ya-Jui Hsieh, Chia-Hao Hsu, Tai-Yu Chen, Yao-Pang Hsu
  • Publication number: 20230065403
    Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Tai-Yu CHEN, Cho-Ying LIN, Sagar Deepak KHIVSARA, Hsiang CHEN, Chieh HSIEH, Sheng-Kang YU, Shang-Chieh CHIEN, Kai Tak LAM, Li-Jui CHEN, Heng-Hsin LIU, Zhiqiang WU
  • Publication number: 20230060899
    Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chieh HSIEH, Tai-Yu CHEN, Cho-Ying LIN, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20230064840
    Abstract: A shutter is provided near the immediate focus of a lithography apparatus in order to deflect tin debris generated by a source side of the apparatus away from a scanner side of the apparatus and towards a debris collection device. The activation of the shutter is synchronized with the generation of light pulses so as not to block light from entering the scanner side.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chieh HSIEH, Tai-Yu CHEN, Hung-Jung HSU, Cho-Ying LIN, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20230046413
    Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.
    Type: Application
    Filed: July 15, 2022
    Publication date: February 16, 2023
    Inventors: Tai-Yu CHEN, Chin-Lai CHEN, Hsiao-Yun CHEN, Wen-Sung HSU, Haw-Kuen SU, Duen-Yi HO, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA
  • Publication number: 20230038668
    Abstract: Example implementations described herein include a laser source and associated methods of operation that can balance or reduce uneven beam profile problem and even improve plasma heating efficiency to enhance conversion efficiency and intensity for extreme ultraviolet radiation generation. The laser source described herein generates an auxiliary laser beam to augment a pre-pulse laser beam and/or a main-pulse laser beam, such that uneven beam profiles may be corrected and/or compensated. This may improve an intensity of the laser source and also improve an energy distribution from the laser source to a droplet of a target material, effective to increase an overall operating efficiency of the laser source.
    Type: Application
    Filed: March 21, 2022
    Publication date: February 9, 2023
    Inventors: Tai-Yu CHEN, Shang-Chieh CHIEN, Sheng-Kang YU, Li-Jui CHEN, Heng-Hsin LIU