Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film provided on one surface of the semiconductor substrate; a first resistance layer including polysilicon provided on the first insulating film; a second insulating film provided on the first resistance layer; a second resistance layer including polysilicon provided on the second insulating film so as to overlap with the first resistance layer; a third insulating film provided on the second resistance layer; a first electrode provided over the third insulating film and electrically connected to the second resistance layer; and a second electrode electrically connected to the first resistance layer, wherein the first resistance layer and the second resistance layer each include a body part and a first contact part having a higher impurity concentration than the body part, and the respective first contact parts are in contact with each other.

Abstract: A resistance element includes a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including a semiconductor substrate, one or more resistance layers on a field insulating film, a pad forming electrode on electrically connected to the one or more resistance layers, a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, electrically connected to another end of at least one of the one or more resistance layers on one end and to a semiconductor substrate on another end, and a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another so as to constitute a resistor as a whole.

Abstract: A semiconductor element includes: a first resistive layer; a second resistive layer provided separately from the first resistive layer and having a resistance value different from that of the first resistive layer; a first external connection electrode electrically connected to one end of the first resistive layer; a second external connection electrode provided separately from the first external connection electrode and electrically connected to one end of the second resistive layer; and a passivation film provided to cover the first and second external connection electrodes and having a first opening and a second opening to which top surfaces of the first and second external connection electrodes are partly exposed, wherein the first opening and the second opening having planar patterns with shapes different from each other.

Abstract: A resistance element includes a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including a semiconductor substrate, one or more resistance layers on a field insulating film, a pad forming electrode on electrically connected to the one or more resistance layers, a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, electrically connected to another end of at least one of the one or more resistance layers on one end and to a semiconductor substrate on another end, and a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another so as to constitute a resistor as a whole.

Abstract: A semiconductor element encompasses a first external electrode on an upper surface side of a semiconductor chip, a second external electrode, spaced apart from the first external electrode, provided in parallel with the first external electrode; and a protective film covering the first and second external electrodes, having first and second windows to expose portions of upper surfaces of the first and second external electrodes, respectively. Planar patterns of the first and second windows are in two-fold rotational symmetry with respect to a center point of an area including the first and second external electrodes and to be asymmetric with respect to a center line between the first and second external electrodes.

Abstract: A resistor element encompasses a first resistive layer, a first protection strip implemented by a tandem connection of p-n junctions, an interlayer insulating film covering the first resistive layer and the first protection strip, a first external electrode on the interlayer insulating film, being connected to a terminal of the first resistive layer and a terminal of the first protection strip, and a second external electrode on the interlayer insulating film, being connected to another terminal of the first resistive layer and another terminal of the first protection strip.

Abstract: A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad.

Abstract: A resistive element includes: a semiconductor substrate; a field insulating film deposited on the semiconductor substrate; a plurality of resistive layers separately deposited on the field insulating film; an interlayer insulating film deposited to cover the field insulating film and the resistive layers; a pad-forming electrode deposited on the interlayer insulating film, and electrically connected to one edges of the resistive layers; a relay wire deposited on the interlayer insulating film separately from the pad-forming electrode, and including a first terminal electrically connected to another edges of the resistive layers and a second terminal provided so as to form an ohmic contact to the semiconductor substrate; and a rear surface electrode provided under the semiconductor substrate to form an ohmic contact to the semiconductor substrate, wherein the resistive element uses, as a resistor, an electric channel between the pad-forming electrode and the rear surface electrode.

Abstract: A dummy element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a first resistive layer deposited on the lower insulating film; an interlayer insulating film covering the first resistive layer; a first pad-forming electrode deposited on the interlayer insulating film so as to be connected to the first resistive layer, and including an extending portion to be in Schottky contact with the semiconductor substrate; a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact; and a counter electrode allocated under the semiconductor substrate, the dummy element simulating a defective state in the lower insulating film and the interlayer insulating film immediately under the first pad-forming electrode included in a corresponding resistive element as a target to be examined.

Abstract: A resistive element includes: a semiconductor substrate; a field insulating film deposited on the semiconductor substrate; a plurality of resistive layers separately deposited on the field insulating film; an interlayer insulating film deposited to cover the field insulating film and the resistive layers; a pad-forming electrode deposited on the interlayer insulating film, and electrically connected to one edges of the resistive layers; a relay wire deposited on the interlayer insulating film separately from the pad-forming electrode, and including a first terminal electrically connected to another edges of the resistive layers and a second terminal provided so as to form an ohmic contact to the semiconductor substrate; and a rear surface electrode provided under the semiconductor substrate to form an ohmic contact to the semiconductor substrate, wherein the resistive element uses, as a resistor, an electric channel between the pad-forming electrode and the rear surface electrode.

Abstract: A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.

Abstract: A resistor element encompasses a first resistive layer, a first protection strip implemented by a tandem connection of p-n junctions, an interlayer insulating film covering the first resistive layer and the first protection strip, a first external electrode on the interlayer insulating film, being connected to a terminal of the first resistive layer and a terminal of the first protection strip, and a second external electrode on the interlayer insulating film, being connected to another terminal of the first resistive layer and another terminal of the first protection strip.

Abstract: A semiconductor element encompasses a first external electrode on an upper surface side of a semiconductor chip, a second external electrode, spaced apart from the first external electrode, provided in parallel with the first external electrode; and a protective film covering the first and second external electrodes, having first and second windows to expose portions of upper surfaces of the first and second external electrodes, respectively. Planar patterns of the first and second windows are in two-fold rotational symmetry with respect to a center point of an area including the first and second external electrodes and to be asymmetric with respect to a center line between the first and second external electrodes.

Abstract: An interlayer insulating film is disposed on a LOCOS oxide film covering an n-type drift region of a JFET. A polysilicon resistor having a spiral planar shape is disposed in the interlayer insulating film. A spiral wire in an outermost circumference of the polysilicon resistor is covered by a source electrode wire that extends on the interlayer insulating film. An end of the polysilicon resistor is electrically connected to a drain electrode wire. A ground terminal wire and a voltage division terminal wire are electrically connected to a spiral wire farther on an inner circumference side by one or more wires than the spiral wire. A portion farther on an inner circumference side than the spiral wire is used as a resistive element, and voltage for an input pad of the JFET is thereby divided to be taken out as a potential of the voltage division terminal wire.

Abstract: A dummy element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a first resistive layer deposited on the lower insulating film; an interlayer insulating film covering the first resistive layer; a first pad-forming electrode deposited on the interlayer insulating film so as to be connected to the first resistive layer, and including an extending portion to be in Schottky contact with the semiconductor substrate; a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact; and a counter electrode allocated under the semiconductor substrate, the dummy element simulating a defective state in the lower insulating film and the interlayer insulating film immediately under the first pad-forming electrode included in a corresponding resistive element as a target to be examined.

Abstract: A semiconductor device includes a p-type semiconductor substrate; an n-type drift layer on the substrate; an n-type drain region in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer; a p-type gate region on the substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern; n-type source regions in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and n-type surge-current guiding-regions in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

Abstract: A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of short-circuit prevention-regions of a second conductivity type at an upper portion of the semiconductor substrate, a first insulating film on a top surface of the semiconductor substrate, a strip-shaped fuse on a top surface of the first insulating film spanning over the short-circuit prevention-regions, a second insulating film on a top surface of the fuse, and a passivation film on a top surface of the second insulating film and having an opening for laser trimming. The opening exposes the second insulating film above an area including the short-circuit prevention-regions.

Abstract: A semiconductor device includes a p-type semiconductor substrate; an n-type drift layer on the substrate; an n-type drain region in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer; a p-type gate region on the substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern; n-type source regions in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and n-type surge-current guiding-regions in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of short-circuit prevention-regions of a second conductivity type at an upper portion of the semiconductor substrate, a first insulating film on a top surface of the semiconductor substrate, a strip-shaped fuse on a top surface of the first insulating film spanning over the short-circuit prevention-regions, a second insulating film on a top surface of the fuse, and a passivation film on a top surface of the second insulating film and having an opening for laser trimming. The opening exposes the second insulating film above an area including the short-circuit prevention-regions.