Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a write element, a read element, a laser, and a near field transducer. An operating thermal gradient of the magnetic media is periodically measured at an operating power setting for the laser that achieves a target magnetic write width. When a slope of the operating thermal gradient exceeds a threshold, a test thermal gradient and magnetic write width of the magnetic media is measured at multiple power settings for the laser in order to detect a contamination of the near field transducer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming a magnetic tunnel junction (MTJ) structure and conformally forming a metal oxide encapsulation layer over and around the MTJ structure. The method further includes removing a portion of the metal oxide encapsulation layer over MTJ structure. Also, the method includes forming a conductive via over and in electrical communication with the top surface of the MTJ structure.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits and/or memory cells are provided. An exemplary method for fabricating integrated circuit includes forming a bottom electrode and forming a fixed layer over the bottom electrode. The fixed layer includes a hard layer over a base layer that includes a seed layer. The seed layer has a thickness of less than about 100 A. Further, the seed layer includes chromium (Cr). The method further includes forming at least a first tunnel barrier layer over the hard layer, forming a storage layer over the first tunnel barrier layer, and forming a top electrode over the storage layer.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits and/or memory cells are provided. An exemplary method for fabricating integrated circuit includes forming a bottom electrode and forming a fixed layer disposed over the bottom electrode. The fixed layer includes a hard layer disposed over a base layer. The base layer includes a seed layer of nickel (Ni) and chromium (Cr) and has a thickness of less than about 100 Angstrom (A). The method further includes forming at least a first tunnel barrier layer over the hard layer, forming a storage layer over the first tunnel barrier layer, and forming a top electrode over the storage layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits and/or memory cells are provided. An exemplary method for fabricating integrated circuit includes forming a bottom electrode and forming a fixed layer disposed over the bottom electrode. The fixed layer includes a hard layer disposed over a base layer. The base layer includes a seed layer of nickel (Ni) and chromium (Cr) and has a thickness of less than about 100 Angstrom (A). The method further includes forming at least a first tunnel barrier layer over the hard layer, forming a storage layer over the first tunnel barrier layer, and forming a top electrode over the storage layer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. A surface smoother, such as a surfactant layer, is provided between the wetting and seed layers. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack comprises a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a ruthenium layer and a synthetic antiferromagnetic (SAF) layer.