Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack includes a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a first magnesium layer and a synthetic antiferromagnetic (SAF) layer.

Abstract: A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. The seed layer includes first and second seed layer separated by a surface smoother, such as a surfactant layer. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: Magnetic tunnel junction (MTJ) storage unit of a memory cell and method of forming thereof are disclosed. The method includes forming a composite bottom electrode on a substrate. The substrate is prepared with a back end dielectric layer. The composite bottom electrode includes a first conductive electrode layer C1 having a first thickness tBE1 and a second conductive electrode layer C2 having a second thickness tBE2. The first and second conductive electrode layers form a bilayer C1/C2. The bilayer is provided to form the composite bottom electrode which enables thinner layers to form the composite bottom electrode. This results in reduced surface roughness to increase tunnel magnetoresistance (TMR) and thermal budget. The method further includes forming a MTJ element. The MTJ element includes a fixed layer and a free layer separated by a tunneling barrier layer. The method also includes forming a top electrode over the MTJ element.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack comprises a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a ruthenium layer and a synthetic antiferromagnetic (SAF) layer.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack includes a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a first magnesium layer and a synthetic antiferromagnetic (SAF) layer.

Abstract: A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. A surface smoother, such as a surfactant layer, is provided between the wetting and seed layers. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

Abstract: A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. The seed layer includes first and second seed layer separated by a surface smoother, such as a surfactant layer. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA). In one aspect, a magnetic element comprises a metal underlayer and a seed layer on the underlayer, the seed layer comprising alternating layers of a first metal and a second metal. The alternating layers of a first metal and a second metal are repeated n times with, 2<=n<=20.

Abstract: A magnetic multilayer stack for a magnetoresistance device and a method of forming the multilayer stack is disclosed. In one aspect, the magnetic multilayer stack comprises a composite soft layer having a non-magnetic layer sandwiched between a first magnetic layer formed of CoFeBN and a second magnetic layer formed of CoFeB.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA). In one aspect, a magnetic element comprises a metal underlayer and a seed layer on the underlayer, the seed layer comprising alternating layers of a first metal and a second metal. The alternating layers of a first metal and a second metal are repeated n times with, 2<=n<=20.

Abstract: A magnetoresistance device is provided. The magnetoresistance device includes a hard magnetic layer, and a soft magnetic layer having a multi-layer stack structure. The multi-layer stack structure has a first layer of a first material and a second layer of a second material. The first material includes cobalt iron boron and the second material includes palladium or platinum.

Abstract: A magnetoresistance device is provided. The magnetoresistance device includes a hard magnetic layer, and a soft magnetic layer having a multi-layer stack structure. The multi-layer stack structure has a first layer of a first material and a second layer of a second material. The first material includes cobalt iron boron and the second material includes a combination of a metallic element and any one of a group consisting of oxygen, nitrogen, carbon and fluorine.