Abstract: A semiconductor device which can avoid increase of a conduction loss of an IGBT, secure a low noise characteristic and also reduce a switch loss. The switching device is of a trench gate type, in which a drift n? layer 110 is exposed to its main surface to a floating p layer 126 and to trench gates. In other words, the floating p layer 126 is provided within the drift n? layer 110 to be spaced from the trench gates.

Abstract: A power semiconductor device having a low loss and a high reliability and a power conversion device using the power semiconductor device are provided. In the power semiconductor device, a plurality of MOS type trench gates are positioned to be spaced by at-least two types of intervals therebetween, a low-resistance floating n+ layer is positioned on a main surface of a semiconductor substrate adjacent to a floating p layer positioned between the adjacent MOS type trench gates having the broad interval to achieve consistency between a low output value and a high breakdown resistance.

Abstract: A fourth semiconductor region of a first conduction type is provided in a partial region of a third semiconductor region of a second conduction type. This configuration enhances the blocking voltage at the time when the sheet carrier concentration of a fifth semiconductor region is enhanced.

Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

Abstract: A power semiconductor device having a low loss and a high reliability and a power conversion device using the power semiconductor device are provided. In the power semiconductor device, a plurality of MOS type trench gates are positioned to be spaced by at-least two types of intervals therebetween, a low-resistance floating n+ layer is positioned on a main surface of a semiconductor substrate adjacent to a floating p layer positioned between the adjacent MOS type trench gates having the broad interval to achieve consistency between a low output value and a high breakdown resistance.

Abstract: A MOSFET including a JFET resistor resultant between a drain region and a channel region caused by depletion of current carriers. Since most of the drain-source voltage is imposed on the JFET resistor, the voltage imposed on a channel region is reduced to prevent concentration of an electric field therein. The JFET resistor adjusts the saturation current of the MOSFET and hence the width of the gate electrode can be sufficiently secured. This also prevents concentration of an electric field onto the channel region. In the MOSFET, the saturation current is reduced while avoiding creation of hot carriers. It is therefore possible to provide an MOSFET suitable for an analog switch.

Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.

Abstract: A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating.