Abstract: An antenna wireless device includes: antenna elements; feed ports respectively corresponding to the antenna elements; one or more detection ports each corresponding to some or all of the plurality of antenna elements; transceiver circuits respectively connected to feed ports; and one or more reference transceiver circuits each connected to a corresponding one or more of the one or more detection ports. For each antenna element, the transceiver circuit processes a first signal to generate a second signal, the second signal fed to the feed port is output to the reference transceiver circuit through the detection port, the reference transceiver circuit processes the second signal to generate a third signal, and detects an amplitude and phase deviation based on the first signal and the third signal, and the transceiver circuit adjusts a phase and an amplitude of a transmission signal based on the amplitude and phase deviation.

Abstract: A wireless communication device includes a baseband variable gain amplifier that amplifies a transmission baseband signal, a local variable gain amplifier that amplifies a local signal, a frequency-conversion circuit that mixes the amplified transmission baseband signal and the amplified local signal to carry out a frequency conversion into a transmission high-frequency signal, a first detector that detects a power of the transmission high-frequency signal, and a controller that controls at least one of a gain of the transmission baseband variable gain amplifier and a gain of the local variable gain amplifier on the basis of the detected power of the transmission high-frequency signal so that a power of the transmission high-frequency signal to be detected takes a predetermined value.

Abstract: A detection calibration circuit includes a first distributor distributing a high frequency input signal, an amplifier amplifying the first high frequency output signal of the first distributor, a second distributor distributing the amplified first high frequency output signal of the first distributor, a reference signal generator outputting a reference signal in accordance with a switchable reference voltage, a switcher selecting a third high frequency output signal of the second distributor or a reference signal of the reference signal generator and outputting the selected signal, a detector detecting the third high frequency output signal of the second distributor or the reference signal of the reference signal generator from the switcher, a sensitivity switcher adjusting a sensitivity for an output signal of the detector, and a calibration control circuit adjusting a detection gain of an input signal of the detector and an input-output sensitivity for an output signal of the detector.

Abstract: A gain control circuit includes: a gain switching controller that changes the gains of a fundamental frequency amplifier and an N-multiplied frequency amplifier; and a detection voltage comparator that determines whether the operating state of an N-multiplier is a saturated operation or a linear operation. The detection voltage comparator determines the operating state of the N-multiplier by comparing an amount of change in a detection signal (first detection signal) representing a fundamental frequency signal with respect to an amount of change in the gain of the fundamental frequency amplifier with an amount of change in a detection signal (second detection signal) representing a high-frequency signal with respect to the amount of change in the gain of the fundamental frequency amplifier. The gain switching controller adjusts the gains of the fundamental frequency amplifier and the N-multiplied frequency amplifier on the basis of the operating state of the N-multiplier.

Abstract: A transformer (2A) outputs differential signals of a positive phase signal (Vout2Ap) having phase ?1+90° and a negative phase signal (Vout2An) having phase ?1?90°. A transformer (2B) outputs differential signals of a positive phase signal (Vout2Bp) having phase ?2+90° and a negative phase signal (Vout2Bn) having phase ?2?90°. An adding circuit (3) composes a pair of differential output signals, as signals corrected in phase error (?1??2) generated in the transformers (2A, 2B), in a manner of summing up vectors of two pairs of the differential signals outputted from the transformers (2A, 2B) for the positive phase signal and the negative phase signal, respectively.

Abstract: A gain control circuit includes: a gain switching controller that changes the gains of a fundamental frequency amplifier and an N-multiplied frequency amplifier; and a detection voltage comparator that determines whether the operating state of an N-multiplier is a saturated operation or a linear operation. The detection voltage comparator determines the operating state of the N-multiplier by comparing an amount of change in a detection signal (first detection signal) representing a fundamental frequency signal with respect to an amount of change in the gain of the fundamental frequency amplifier with an amount of change in a detection signal (second detection signal) representing a high-frequency signal with respect to the amount of change in the gain of the fundamental frequency amplifier. The gain switching controller adjusts the gains of the fundamental frequency amplifier and the N-multiplied frequency amplifier on the basis of the operating state of the N-multiplier.

Abstract: A wireless communication device includes a baseband variable gain amplifier that amplifies a transmission baseband signal, a local variable gain amplifier that amplifies a local signal, a frequency-conversion circuit that mixes the amplified transmission baseband signal and the amplified local signal to carry out a frequency conversion into a transmission high-frequency signal, a first detector that detects a power of the transmission high-frequency signal, and a controller that controls at least one of a gain of the transmission baseband variable gain amplifier and a gain of the local variable gain amplifier on the basis of the detected power of the transmission high-frequency signal so that a power of the transmission high-frequency signal to be detected takes a predetermined value.

Abstract: A balun converts a single-ended radio-frequency signal into differential signals. A differential matching circuit outputs a maximum-level positive-phase output signal at a lower or higher frequency than the center frequency and outputs a maximum-level reverse-phase output signal at a higher or lower frequency than the center frequency. An amplification circuit amplifies a positive-phase output signal and a reverse-phase output signal of the differential matching circuit. A mixing circuit converts the positive-phase output signal and the reverse-phase output signal that are output from the amplification circuit into intermediate-frequency signals using locally generated signals.

Abstract: A detection calibration circuit includes a first distributor distributing a high frequency input signal, an amplifier amplifying the first high frequency output signal of the first distributor, a second distributor distributing the amplified first high frequency output signal of the first distributor, a reference signal generator outputting a reference signal in accordance with a switchable reference voltage, a switcher selecting a third high frequency output signal of the second distributor or a reference signal of the reference signal generator and outputting the selected signal, a detector detecting the third high frequency output signal of the second distributor or the reference signal of the reference signal generator from the switcher, a sensitivity switcher adjusting a sensitivity for an output signal of the detector, and a calibration control circuit adjusting a detection gain of an input signal of the detector and an input-output sensitivity for an output signal of the detector.

Abstract: A balun converts a single-ended radio-frequency signal into differential signals. A differential matching circuit outputs a maximum-level positive-phase output signal at a lower or higher frequency than the center frequency and outputs a maximum-level reverse-phase output signal at a higher or lower frequency than the center frequency. An amplification circuit amplifies a positive-phase output signal and a reverse-phase output signal of the differential matching circuit. A mixing circuit converts the positive-phase output signal and the reverse-phase output signal that are output from the amplification circuit into intermediate-frequency signals using locally generated signals.

Abstract: A reception signal processing devices includes a converter which converts an analog signal amplified by an amplifying section to a digital signal, switches respectively provided in post-stages of variable gain amplifiers of the amplifying section, a bypass switch section which sets to open and close a path in which outputs of the variable gain amplifiers go around the variable gain amplifiers of the post-stages and are inputted to the converter, a switch controller which controls the switches and the bypass switch section and a DC offset controller which sets a correction value of a DC offset in accordance with a gain set to the variable gain amplifier as an object to be corrected.

Abstract: An A/D conversion device generates a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal. A shift voltage is generated which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle. An analog signal is offset by the shift voltage. The offset analog signal is converted to a digital signal every cycle of the reference clock signal. Outputs from the A/D converter are averaged every cycle of the control clock signal.

Abstract: A transformer (2A) outputs differential signals of a positive phase signal (Vout2Ap) having phase ?1+90° and a negative phase signal (Vout2An) having phase ?1?90°. A transformer (2B) outputs differential signals of a positive phase signal (Vout2Bp) having phase ?2+90° and a negative phase signal (Vout2Bn) having phase ?2?90°. An adding circuit (3) composes a pair of differential output signals, as signals corrected in phase error (?1??2) generated in the transformers (2A, 2B), in a manner of summing up vectors of two pairs of the differential signals outputted from the transformers (2A, 2B) for the positive phase signal and the negative phase signal, respectively.

Abstract: A reception signal processing devices includes a converter which converts an analog signal amplified by an amplifying section to a digital signal, switches respectively provided in post-stages of variable gain amplifiers of the amplifying section, a bypass switch section which sets to open and close a path in which outputs of the variable gain amplifiers go around the variable gain amplifiers of the post-stages and are inputted to the converter, a switch controller which controls the switches and the bypass switch section and a DC offset controller which sets a correction value of a DC offset in accordance with a gain set to the variable gain amplifier as an object to be corrected.

Abstract: An A/D conversion device has means for generating a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal; means for generating a shift voltage which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle, means for offsetting an analog signal by the shift voltage, means for A/D converting the offset analog signal every cycle of the reference clock signal signal, and means for averaging outputs from the A/D converter every cycle of the control clock signal.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).

Abstract: In a clock signal generation apparatus, a clock signal delay calculation section has a delay detection circuit for monitoring the delay characteristics of the variable delay circuits of a clock signal generation circuit due to external variation factors and calculates the delay amounts of N-phase clock signals, and a clock signal delay control section varies the delay amounts of the variable delay circuits on the basis of delay variation data, external variation factors being used as parameters thereof, stored in a delay variation data section and the calculated delay amounts of the N-phase clock signals. In the case that, for example, clock signals required for a discrete-time circuit have changed due to external variation factors, such as power supply voltage and environmental temperature, the non-overlap times and the duty ratios of the clock signals required for the discrete-time circuit can be set to optimal values.