Abstract: A semiconductor device includes a semiconductor substrate, an insulation film formed on the semiconductor substrate, a film formed on the insulation film having a side wall, and a side wall film formed on the insulation film so as to surround the side wall of the film. The side wall film has a slope and satisfies a condition a>d, where a is a width of a bottom surface of the side wall film which is in contact with the insulation film, and d is a thickness of the film.

Abstract: A method for fabricating a dynamic random access memory comprises the steps of determining a design rule for word lines and bit lines and further for a pattern that extends from a memory cell array region to a peripheral region across a stepped boundary, determining a step height of the stepped boundary based upon the design rule, determining a capacitance of the memory cell capacitor based upon the step height of the stepped boundary, determining a parasitic capacitance of a bit line such that a ratio of the parasitic capacitance to the capacitance of the memory cell is smaller than a predetermined factor, and determining the number of the memory cells that are connected to one bit line based upon the parasitic capacitance of the bit line.

Abstract: In forming a semiconductor integrated circuit device, a field insulation film is formed on a substrate using a selective thermal oxidation process whereby openings are formed in the insulation film thereby exposing the substrate at certain predetermined active regions. A patterned insulation film is formed on the field insulation film so as to present contact holes corresponding to the openings in the field insulation film. Each of the contact holes has a first pair of opposed edges extending in a first direction and defined by interior edges of the field insulation film and a second pair of opposed edges extending in a second direction and defined by edges of the patterned insulation film. The resultant structure provides a reduced pitch of the contact holes in the second direction.

Abstract: A dynamic random access memory (DRAM) device includes: a plurality of sense amplifiers; bit lines connected to the amplifiers, respectively; a first group of memory cells arranged in a row and connected to one of the bit lines; and a second group of memory cells arranged in a row and connected to the same bit line; the first and second groups being arranged side by side and adjacently to each other, shifted one from the other by a half of a memory cell pitch, and connected alternately to each other in an open bit line system.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, and first and second word lines extending generally parallel to each other along a predetermined direction and respectively coupled to gate electrodes of the first and second transfer transistors. Each of the first and second thin film transistor loads include first and second impurity regions which sandwich a channel region formed by a semiconductor layer provided on the semiconductor substrate, and a gate electrode formed by confronting conductor layers and isolated from the channel region.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, where each of the first and second transfer transistors, the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected.

Abstract: A non-volatile memory device includes a semiconductor layer, floating gates, control gates, pairs of first and second impurity diffused layers formed in the semiconductor layer and located on both sides of the control gates Word lines are electrically connected to the control gates, and bit lines are electrically connected to the first impurity diffused layers and perpendicular to the word lines Wiring electrodes are electrically connected to the second impurity diffused layers, and run in a direction in which the bit lines run. Areas including the pairs of first and second impurity diffused areas are obliquely arranged with respect to the bit lines.

Abstract: Semiconductor devices and methods for producing semiconductor devices to be produced by conducting a combination of a step for producing a gate elctrode of a first conductor layer which is piled on a gate insulator, a step for producing a drain region which is connected with an n.sup.+ -region located under the gate electrode by employing the gate electrode as a part of the mask, and a step for piling, on or over the gate electrode, a second conductor layer connected with the n.sup.+ -region through a contact hole produced in the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate and having a first source diffusion region, a first drain diffusion region and a first gate electrode, a second transistor formed on the semiconductor substrate adjacent to the first transistor and having a second source diffusion region, a second drain diffusion region and a second gate electrode, a field oxide layer formed on the semiconductor substrate for isolating the first and second transistors, a first insulator layer which covers a surface of the semiconductor substrate including a surface of the first transistor but excluding a surface of the second transistor, where the first insulator layer has a side wall portion, and a second insulator layer formed at the side wall portion of the first insulator layer and a side wall portion of the second gate electrode of the second transistor.

Abstract: A flash-type nonvolatile semiconductor memory having a precise erasing level is disclosed. The memory of the present invention includes a plurality of source lines arranged in parallel to bit lines in correspondence with columns of a cell matrix, a plurality of level judging circuits arranged at each bit line and a plurality of source line switches arranged at each source line. In an erasing operation, memory cells are erased so as to not generate over-erased cells, every selected memory cell is simultaneously tested whether or not it has a threshold less than a upper limit of an object range, and only unsufficiently erased memory cells are further erased in a re-erasing step by being controlled with the source line switches.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a field insulation film formed on a surface of the semiconductor substrate by a selective thermal oxidation process employing an oxidation-resistant mask whereby first and second groups of openings are formed therein for exposing the substrate at predetermined locations respectively corresponding to first and second active regions and relative to which first and second groups of contact holes are to be formed.

Abstract: A semiconductor device comprises:a insulating film having a first part and a second part, the second part being thiner than the first part; and a polycrystalline silicon film having a first part arranged over the first part of the insulating film and a second part arranged over the second part of the insulating film, the second part of the polycrystalline silicon film having a lower concentration of impurities than that of the first part of the polycrystalline silicon film.

Abstract: A method for fabricating a semiconductor device comprises the steps of defining a plurality of regions on a substrate, exposing a first pattern that extends over a plurality of such regions such that the first pattern is exposed on the plurality of regions simultaneously, and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of the plurality of regions.

Abstract: A cell array of non-volatile memory semiconductor memory device includes a semiconductor substrate having a first conduction type, a first insulating film formed on the semiconductor substrate, and a plurality of active regions formed in the semiconductor substrate, each of the active regions having a second conduction type opposite to the first conduction type. The cell array also includes a plurality of floating gate electrodes formed on the first insulating film, a second insulating film covering the floating gate electrodes, a plurality of control gate electrodes which are formed on the second insulating film and which run above the floating gate electrodes, and bit lines electrically coupled to the active regions. Each of the active regions has a substantially H-shaped surface portion close to adjacent four of the floating gate electrodes.

Abstract: An electrically erasable and programmable read only memory includes a memory cell array having a plurality of memory cells coupled to bit lines and word lines. Each of the memory cells includes a select transistor controlled by one of the word lines, a memory transistor of the enhancement type coupled to one of the bit lines through the select transistor and having a control gate, and a drive transistor having a gate coupled to the one of the word lines and applying a control gate voltage supplied through a program line to the control gate of the memory transistor. Further, the electrically erasable and programmable read only memory includes a select device for selecting at least one of the bit lines and one of the word lines on the basis of an address supplied from an external device, and a sense amplifier for outputting data stored in the memory cell array.

Abstract: A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

Abstract: A semiconductor device includes a semiconductor substrate, an insulation film formed on the semiconductor substrate, a film formed on the insulation film having a side wall, and a side wall film formed on the insulation film so as to surround the side wall of the film. The side wall film has a slope and satisfies a condition a>d, where a is a width of a bottom surface of the side wall film which is in contact with the insulation film, and d is a thickness of the film.

Abstract: A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on a lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

Abstract: A semiconductor memory device comprises first sense amplifier driving lines and second sense amplifier driving lines, the first sense amplifier driving lines are formed in a first wiring layer along the word line direction, and the second sense amplifier driving lines are formed in a second wiring layer along the bit line direction. Therefore, a current flowing in the each of the first sense amplifier driving lines becomes small, and the width of the first sense amplifier driving lines becomes small, so that occupancy area of the semiconductor memory device can be decreased and a large scale integration can be realized.

Abstract: A dynamic random access memory device includes a substrate, a plurality of pairs of sources and drains of transistors formed in the substrate and located within an area defined by field oxidation films formed on the substrate. Gate electrodes are formed on gate oxidation films formed on the substrate and located between the pairs of sources and drains. The gate electrodes extend in a first direction perpendicular to the direction of a channel formed between the paired source and drain. A plurality of word lines are formed on the field oxidation films and extend in a second direction identical to the direction of the channel. The word lines are integrally formed with the gate electrodes. A plurality of bit lines are formed in the substrate and include the sources as portions thereof. The bit lines extend in the first direction perpendicular to the direction of the channel. An insulating film covers the word lines and the gate electrodes, and includes contact holes.